[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Make use of Intel SPI common block

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22361


Change subject: soc/intel/skylake: Make use of Intel SPI common block
......................................................................

soc/intel/skylake: Make use of Intel SPI common block

TEST=Build and boot soraka/eve

Signed-off-by: Subrata Banik <subrata.banik at intel.com>
Change-Id: I10de3ff75a3b063c4c46471e380bbbe2630c35f3
---
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/Makefile.inc
D src/soc/intel/skylake/spi.c
3 files changed, 1 insertion(+), 73 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/22361/1

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index f830f54..9f8dfe5 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -73,6 +73,7 @@
 	select SOC_INTEL_COMMON_BLOCK_SCS
 	select SOC_INTEL_COMMON_BLOCK_SGX
 	select SOC_INTEL_COMMON_BLOCK_SMBUS
+	select SOC_INTEL_COMMON_BLOCK_SPI
 	select SOC_INTEL_COMMON_BLOCK_TIMER
 	select SOC_INTEL_COMMON_BLOCK_UART
 	select SOC_INTEL_COMMON_BLOCK_XHCI
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index bc53922..e3a4eda 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -20,7 +20,6 @@
 bootblock-y += gspi.c
 bootblock-y += pch.c
 bootblock-y += pmutil.c
-bootblock-y += spi.c
 bootblock-y += lpc.c
 
 verstage-y += gspi.c
@@ -28,7 +27,6 @@
 verstage-$(CONFIG_UART_DEBUG) += uart_debug.c
 verstage-y += pmutil.c
 verstage-y += i2c.c
-verstage-y += spi.c
 
 romstage-y += gpio.c
 romstage-y += gspi.c
@@ -39,7 +37,6 @@
 romstage-y += pei_data.c
 romstage-y += pmutil.c
 romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
-romstage-y += spi.c
 romstage-$(CONFIG_UART_DEBUG) += uart_debug.c
 
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
@@ -66,7 +63,6 @@
 ramstage-y += sd.c
 ramstage-y += smi.c
 ramstage-y += smmrelocate.c
-ramstage-y += spi.c
 ramstage-y += systemagent.c
 ramstage-y += uart.c
 ramstage-$(CONFIG_UART_DEBUG) += uart_debug.c
@@ -77,14 +73,12 @@
 smm-y += pch.c
 smm-y += pmutil.c
 smm-y += smihandler.c
-smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
 smm-$(CONFIG_UART_DEBUG) += uart_debug.c
 smm-y += uart.c
 
 postcar-y += memmap.c
 postcar-$(CONFIG_UART_DEBUG) += uart_debug.c
 postcar-y += gspi.c
-postcar-y += spi.c
 
 # cpu_microcode_bins += ???
 
diff --git a/src/soc/intel/skylake/spi.c b/src/soc/intel/skylake/spi.c
deleted file mode 100644
index e575e6e..0000000
--- a/src/soc/intel/skylake/spi.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2016 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <device/spi.h>
-#include <intelblocks/fast_spi.h>
-#include <intelblocks/gspi.h>
-#include <soc/ramstage.h>
-#include <spi-generic.h>
-
-const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
-	{ .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 },
-#if !ENV_SMM
-	{ .ctrlr = &gspi_ctrlr, .bus_start = 1,
-	  .bus_end =  1 + (CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX - 1)},
-#endif
-};
-
-const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
-
-#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__)
-
-static int spi_dev_to_bus(struct device *dev)
-{
-	return spi_devfn_to_bus(dev->path.pci.devfn);
-}
-
-static struct spi_bus_operations spi_bus_ops = {
-	.dev_to_bus			= &spi_dev_to_bus,
-};
-
-static struct device_operations spi_dev_ops = {
-	.read_resources			= &pci_dev_read_resources,
-	.set_resources			= &pci_dev_set_resources,
-	.enable_resources		= &pci_dev_enable_resources,
-	.scan_bus			= &scan_generic_bus,
-	.ops_pci			= &soc_pci_ops,
-	.ops_spi_bus			= &spi_bus_ops,
-};
-
-static const unsigned short pci_device_ids[] = {
-	0x9d24, 0x9d29, 0x9d2a, 0
-};
-
-static const struct pci_driver pch_spi __pci_driver = {
-	.ops				= &spi_dev_ops,
-	.vendor				= PCI_VENDOR_ID_INTEL,
-	.devices			= pci_device_ids,
-};
-#endif

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I10de3ff75a3b063c4c46471e380bbbe2630c35f3
Gerrit-Change-Number: 22361
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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