[coreboot-gerrit] Change in coreboot[master]: util/inteltool: Add PCIEXBAR and PXPEPBAR reading for Skylake

[Maximilian Schander (Code Review)]

Maximilian Schander has uploaded a new patch set (#2). ( https://review.coreboot.org/22350 )

Change subject: util/inteltool: Add PCIEXBAR and PXPEPBAR reading for Skylake
......................................................................

util/inteltool: Add PCIEXBAR and PXPEPBAR reading for Skylake

Both registers behave the same as on the previous generation

Taken from
 * 6th Generation Intel Processor Families for S-Platform
     Volume 2 of 2
 * Page 55 and 62
 * 332688-003EN

Change-Id: Id02a38a7ab51003c9d0f16ebb2300a16b66a15f9
Signed-off-by: Maximilian Schander <coreboot at mimoja.de>
---
M util/inteltool/pcie.c
1 file changed, 4 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/22350/2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Id02a38a7ab51003c9d0f16ebb2300a16b66a15f9
Gerrit-Change-Number: 22350
Gerrit-PatchSet: 2
Gerrit-Owner: Maximilian Schander <coreboot at mimoja.de>
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