[coreboot-gerrit] Change in coreboot[master]: drvs/lenovo/hybrid_graphics/romstage: Fix switching while on power

Patrick Rudolph (Code Review) gerrit at coreboot.org
Sat Nov 4 20:16:29 CET 2017


Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/22341


Change subject: drvs/lenovo/hybrid_graphics/romstage: Fix switching while on power
......................................................................

drvs/lenovo/hybrid_graphics/romstage: Fix switching while on power

Don't assume default values in PMH7 on boot.

Change-Id: I30ec19e13269cb254e51ad1fab3b10ad1a49e86e
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
M src/drivers/lenovo/hybrid_graphics/romstage.c
1 file changed, 18 insertions(+), 3 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/22341/1

diff --git a/src/drivers/lenovo/hybrid_graphics/romstage.c b/src/drivers/lenovo/hybrid_graphics/romstage.c
index 9009c58..e46b7f6 100644
--- a/src/drivers/lenovo/hybrid_graphics/romstage.c
+++ b/src/drivers/lenovo/hybrid_graphics/romstage.c
@@ -77,13 +77,28 @@
 
 	/*
 	 * Need to do power handling here as we know there's a dGPU to
-	 * turn off. Support GPIO and Thinker1.
+	 * turn on/off. Support GPIO and Thinker1.
 	 */
-	if (!*enable_peg) {
+	if (*enable_peg) {
+		if (config->has_dgpu_power_gpio) {
+			set_gpio(config->dgpu_power_gpio,
+				~config->dgpu_power_off_lvl);
+		} else if (config->has_thinker1 &&
+			   !(pmh7_register_read(0x50) & 0x08)) {
+			pmh7_register_set_bit(0x50, 3); // DGPU_PWR
+			pmh7_register_clear_bit(0x50, 7); // DGPU_RST
+			mdelay(10);
+			pmh7_register_set_bit(0x50, 7); // DGPU_RST
+		} else {
+			printk(BIOS_ERR, "Hybrid graphics:"
+			       " FIXME: dGPU power not enabled !\n");
+		}
+	} else {
 		if (config->has_dgpu_power_gpio) {
 			set_gpio(config->dgpu_power_gpio,
 				 config->dgpu_power_off_lvl);
-		} else if (config->has_thinker1) {
+		} else if (config->has_thinker1 &&
+			   (pmh7_register_read(0x50) & 0x08)) {
 			pmh7_register_clear_bit(0x50, 7); // DGPU_RST
 			udelay(100);
 			pmh7_register_clear_bit(0x50, 3); // DGPU_PWR

-- 
To view, visit https://review.coreboot.org/22341
To unsubscribe, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I30ec19e13269cb254e51ad1fab3b10ad1a49e86e
Gerrit-Change-Number: 22341
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro at das-labor.org>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20171104/ecb9334e/attachment.html>


More information about the coreboot-gerrit mailing list