[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Add northbridge register macros

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22339


Change subject: amd/stoneyridge: Add northbridge register macros
......................................................................

amd/stoneyridge: Add northbridge register macros

Add helpers for determining the D18F1 offset for MMIO base and limit,
and I/O base/limit registers.

Change-Id: I3f61bff00b8f3ada3e1bbfb163e1f223708bd47d
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/stoneyridge/include/soc/northbridge.h
1 file changed, 20 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/22339/1

diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h
index 9113878..5cf911e 100644
--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h
@@ -26,15 +26,35 @@
 # define CPU_CNT_MASK		0x1f /*  CpuCnt + 1 = no. CPUs */
 
 /* D18F1 - Address Map Registers */
+
+/* MMIO base and limit */
 #define D18F1_MMIO_BASE0_LO	0x80
 # define MMIO_WE		(1 << 1)
 # define MMIO_RE		(1 << 0)
 #define D18F1_MMIO_LIMIT0_LO	0x84
 # define MMIO_NP		(1 << 7)
+#define D18F1_MMIO_BASELIM0_HI	0x180
+#define D18F1_MMIO_BASE8_LO	0x1a0
+#define D18F1_MMIO_LIMIT8_LO	0x1a4
+#define D18F1_MMIO_BASELIM8_HI	0x1c0
+#define NB_MMIO_BASE_LO(reg)	((reg) * 2 * sizeof(uint32_t) + ((reg < 8) \
+					? D18F1_MMIO_BASE0_LO \
+					: D18F1_MMIO_BASE8_LO \
+						- 8 * sizeof(uint64_t)))
+#define NB_MMIO_LIMIT_LO(reg)	(NB_MMIO_BASE_LO(reg) + sizeof(uint32_t))
+#define NB_MMIO_BASELIM_HI(reg)	((reg) * sizeof(uint32_t) + ((reg < 8) \
+					? D18F1_MMIO_BASELIM0_HI \
+					: D18F1_MMIO_BASELIM8_HI \
+						- 8 * sizeof(uint32_t)))
+/* I/O base and limit */
 #define D18F1_IO_BASE0		0xc0
 # define IO_WE			(1 << 1)
 # define IO_RE			(1 << 0)
 #define D18F1_IO_LIMIT0		0xc4
+#define NB_IO_BASE(reg)		((reg) * 2 * sizeof(uint32_t) + D18F1_IO_BASE0)
+#define NB_IO_LIMIT(reg)	(NB_IO_BASE(reg) + sizeof(uint32_t))
+
+
 #define D18F1_DRAM_HOLE		0xf0
 # define DRAM_HOIST_VALID	(1 << 1)
 # define DRAM_HOLE_VALID	(1 << 0)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I3f61bff00b8f3ada3e1bbfb163e1f223708bd47d
Gerrit-Change-Number: 22339
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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