[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge/peg: Add PEG driver
Patrick Rudolph (Code Review)
gerrit at coreboot.org
Sat Nov 4 16:24:31 CET 2017
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/22337
Change subject: nb/intel/sandybridge/peg: Add PEG driver
......................................................................
nb/intel/sandybridge/peg: Add PEG driver
Required for other ACPI generators, like the one used for _ROM.
* Add ACPI code for PEG10/PEG11/PEG12/PEG60 and include it on all platforms.
* Add PCIe driver for PEG. The driver returns ACPI names for ssdt generators
and includes an ACPI generator to write _STA method.
Needs test on real hardware.
Change-Id: I96835c43522580c95fd4f250c56bf9438e993bc1
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
M src/northbridge/intel/sandybridge/Makefile.inc
A src/northbridge/intel/sandybridge/acpi/peg.asl
M src/northbridge/intel/sandybridge/acpi/sandybridge.asl
A src/northbridge/intel/sandybridge/pcie.c
4 files changed, 250 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/22337/1
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc
index 846d31b..a2ab06d 100644
--- a/src/northbridge/intel/sandybridge/Makefile.inc
+++ b/src/northbridge/intel/sandybridge/Makefile.inc
@@ -17,6 +17,7 @@
ramstage-y += ram_calc.c
ramstage-y += northbridge.c
+ramstage-y += pcie.c
ramstage-y += gma.c
ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_sandybridge_lvds.c
ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c
diff --git a/src/northbridge/intel/sandybridge/acpi/peg.asl b/src/northbridge/intel/sandybridge/acpi/peg.asl
new file mode 100644
index 0000000..b9b6a23
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/acpi/peg.asl
@@ -0,0 +1,131 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Patrick Rudolph <siro at das-labor.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (PEGP)
+{
+ Name (_ADR, 0x00010000)
+
+ // PCI Interrupt Routing.
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (PICM) {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, 0, 16 },
+ Package() { 0x0000ffff, 1, 0, 17 },
+ Package() { 0x0000ffff, 2, 0, 18 },
+ Package() { 0x0000ffff, 3, 0, 19 }
+ })
+ } Else {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }
+ })
+ }
+ }
+
+ Device (DEV0) {
+ Name(_ADR, 0x00000000)
+ }
+}
+
+Device (PEG1)
+{
+ Name (_ADR, 0x00010001)
+
+ // PCI Interrupt Routing.
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (PICM) {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, 0, 16 },
+ Package() { 0x0000ffff, 1, 0, 17 },
+ Package() { 0x0000ffff, 2, 0, 18 },
+ Package() { 0x0000ffff, 3, 0, 19 }
+ })
+ } Else {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }
+ })
+ }
+ }
+
+ Device (DEV0) {
+ Name(_ADR, 0x00000000)
+ }
+}
+
+Device (PEG2)
+{
+ Name (_ADR, 0x00010002)
+
+ // PCI Interrupt Routing.
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (PICM) {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, 0, 16 },
+ Package() { 0x0000ffff, 1, 0, 17 },
+ Package() { 0x0000ffff, 2, 0, 18 },
+ Package() { 0x0000ffff, 3, 0, 19 }
+ })
+ } Else {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }
+ })
+ }
+ }
+
+ Device (DEV0) {
+ Name(_ADR, 0x00000000)
+ }
+}
+
+Device (PEG6)
+{
+ Name (_ADR, 0x00060000)
+
+ // PCI Interrupt Routing.
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (PICM) {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, 0, 16 },
+ Package() { 0x0000ffff, 1, 0, 17 },
+ Package() { 0x0000ffff, 2, 0, 18 },
+ Package() { 0x0000ffff, 3, 0, 19 }
+ })
+ } Else {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }
+ })
+ }
+ }
+
+ Device (DEV0) {
+ Name(_ADR, 0x00000000)
+ }
+}
\ No newline at end of file
diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
index 609106f..301ee8a 100644
--- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
+++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
@@ -16,6 +16,7 @@
#include "../sandybridge.h"
#include "hostbridge.asl"
+#include "peg.asl"
/* PCI Device Resource Consumption */
Device (PDRC)
diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c
new file mode 100644
index 0000000..743d8cb
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/pcie.c
@@ -0,0 +1,117 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Patrick Rudolph <siro at das-labor.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pciexp.h>
+#include <device/pci_ids.h>
+#include <assert.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+
+#include "sandybridge.h"
+
+static void pcie_disable(struct device *dev)
+{
+ printk(BIOS_INFO, "%s: Disabling device\n", dev_path(dev));
+ dev->enabled = 0;
+}
+
+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+static const char *pcie_acpi_name(const struct device *dev)
+{
+ ASSERT(dev);
+ ASSERT(dev->bus);
+
+ if (dev->path.type != DEVICE_PATH_PCI)
+ return NULL;
+
+ if (dev->bus->secondary == 0)
+ switch (dev->path.pci.devfn) {
+ case PCI_DEVFN(1, 0):
+ return "PEGP";
+ case PCI_DEVFN(1, 1):
+ return "PEG1";
+ case PCI_DEVFN(1, 2):
+ return "PEG2";
+ case PCI_DEVFN(6, 0):
+ return "PEG6";
+ };
+
+ const device_t port = dev->bus->dev;
+ ASSERT(port);
+ ASSERT(port->bus);
+
+ if (dev->path.pci.devfn == PCI_DEVFN(0, 0) &&
+ port->bus->secondary == 0 &&
+ (port->path.pci.devfn == PCI_DEVFN(1, 0) ||
+ port->path.pci.devfn == PCI_DEVFN(1, 1) ||
+ port->path.pci.devfn == PCI_DEVFN(1, 2) ||
+ port->path.pci.devfn == PCI_DEVFN(6, 0)))
+ return "DEV0";
+
+ return NULL;
+}
+
+static void pcie_ssdt(struct device *dev)
+{
+ acpigen_write_scope(acpi_device_name(dev));
+ acpigen_write_STA(dev->enabled);
+ acpigen_pop_len(); /* pop scope */
+}
+#endif
+
+static void
+pcie_set_subsystem(struct device *dev, unsigned int ven, unsigned int device)
+{
+ /* NOTE: This is not the default position! */
+ if (!ven || !device)
+ pci_write_config32(dev, 0x94,
+ pci_read_config32(dev, 0));
+ else
+ pci_write_config32(dev, 0x94,
+ ((device & 0xffff) << 16) | (ven & 0xffff));
+}
+
+static struct pci_operations pci_ops = {
+ .set_subsystem = pcie_set_subsystem,
+};
+
+static struct device_operations device_ops = {
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .scan_bus = pciexp_scan_bridge,
+ .reset_bus = pci_bus_reset,
+ .disable = pcie_disable,
+ .init = pci_dev_init,
+ .ops_pci = &pci_ops,
+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+ .acpi_name = pcie_acpi_name,
+ .acpi_fill_ssdt_generator = pcie_ssdt,
+#endif
+};
+
+static const unsigned short pci_device_ids[] = { 0x0101, 0x0105, 0x0109, 0x010d,
+ 0x0151, 0x0155, 0x0159, 0x015d,
+ 0 };
+
+static const struct pci_driver pch_pcie __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};
--
To view, visit https://review.coreboot.org/22337
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I96835c43522580c95fd4f250c56bf9438e993bc1
Gerrit-Change-Number: 22337
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro at das-labor.org>
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