[coreboot-gerrit] Change in coreboot[master]: gru: Fix and export SPK_PA_EN GPIO for Scarlet

[Julius Werner (Code Review)]

Hello Philip Chen,

I'd like you to do a code review. Please visit

    https://review.coreboot.org/22323

to review the following change.


Change subject: gru: Fix and export SPK_PA_EN GPIO for Scarlet
......................................................................

gru: Fix and export SPK_PA_EN GPIO for Scarlet

On older Grus, GPIO0_A2 was an audio voltage rail enable line. On
Scarlet, we instead moved the audio codec enable (previously on
GPIO1_A2) there. Unfortunately the code still had some hardcoded
leftovers that were overlooked in the initial port and make our speakers
smell weird.

This patch fixes the incorrect GPIO settings and adds the speaker enable
pin to the GPIOs passed through the coreboot table, so that depthcharge
doesn't have to keep its own definition of the pin which may go out of
sync.

Change-Id: I1ac70ee47ebf04b8b92ff17a46cbf5d839421a61
Signed-off-by: Julius Werner <jwerner at chromium.org>
---
M src/mainboard/google/gru/board.h
M src/mainboard/google/gru/chromeos.c
M src/mainboard/google/gru/mainboard.c
3 files changed, 6 insertions(+), 5 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/22323/1

diff --git a/src/mainboard/google/gru/board.h b/src/mainboard/google/gru/board.h
index 7237d46..f95db57 100644
--- a/src/mainboard/google/gru/board.h
+++ b/src/mainboard/google/gru/board.h
@@ -31,6 +31,7 @@
 #define GPIO_P15V_EN	dead_code_t(gpio_t, "PP1500 doesn't exist on Scarlet")
 #define GPIO_P18V_AUDIO_PWREN dead_code_t(gpio_t, "doesn't exist on Scarlet")
 #define GPIO_P30V_EN	GPIO(0, B, 1)
+#define GPIO_SPK_PA_EN	GPIO(0, A, 2)
 #define GPIO_TP_RST_L	dead_code_t(gpio_t, "don't need TP_RST_L on Scarlet")
 #define GPIO_TPM_IRQ	GPIO(1, C, 1)
 #define GPIO_WP		GPIO(0, B, 5)
@@ -41,6 +42,7 @@
 #define GPIO_P15V_EN	GPIO(0, B, 2)
 #define GPIO_P18V_AUDIO_PWREN GPIO(0, A, 2)
 #define GPIO_P30V_EN	GPIO(0, B, 4)
+#define GPIO_SPK_PA_EN	GPIO(1, A, 2)
 #define GPIO_TP_RST_L	GPIO(3, B, 4)	/* may also be an I2C pull-up enable */
 #define GPIO_TPM_IRQ	GPIO(0, A, 5)
 #define GPIO_WP		GPIO(1, C, 2)
diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c
index b28e9fc..0dd03ea 100644
--- a/src/mainboard/google/gru/chromeos.c
+++ b/src/mainboard/google/gru/chromeos.c
@@ -36,6 +36,7 @@
 		{GPIO_EC_IN_RW.raw, ACTIVE_HIGH, -1, "EC in RW"},
 		{GPIO_EC_IRQ.raw, ACTIVE_LOW, -1, "EC interrupt"},
 		{GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"},
+		{GPIO_SPK_PA_EN.raw, ACTIVE_HIGH, -1, "speaker enable"},
 #if IS_ENABLED(CONFIG_GRU_HAS_TPM2)
 		{GPIO_TPM_IRQ.raw, ACTIVE_HIGH, -1, "TPM interrupt"},
 #endif
diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c
index 43fbb71..3721ce8 100644
--- a/src/mainboard/google/gru/mainboard.c
+++ b/src/mainboard/google/gru/mainboard.c
@@ -226,11 +226,9 @@
 	/* AUDIO IO domain 1.8V voltage selection */
 	write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 1));
 
-	/* CPU1_P1.8V_AUDIO_PWREN for P1.8_AUDIO */
-	gpio_output(GPIO(0, A, 2), 1);
-
-	/* set CPU1_SPK_PA_EN output */
-	gpio_output(GPIO(1, A, 2), 0);
+	if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_SCARLET))
+		gpio_output(GPIO_P18V_AUDIO_PWREN, 1);
+	gpio_output(GPIO_SPK_PA_EN, 0);
 
 	rkclk_configure_i2s(12288000);
 }

-- 
To view, visit https://review.coreboot.org/22323
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I1ac70ee47ebf04b8b92ff17a46cbf5d839421a61
Gerrit-Change-Number: 22323
Gerrit-PatchSet: 1
Gerrit-Owner: Julius Werner <jwerner at chromium.org>
Gerrit-Reviewer: Philip Chen <philipchen at chromium.org>
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