[coreboot-gerrit] Change in coreboot[master]: google/reks: override RX ODT limit, RAM geometry if needed

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/22268


Change subject: google/reks: override RX ODT limit, RAM geometry if needed
......................................................................

google/reks: override RX ODT limit, RAM geometry if needed

Adapted from Chromium commit 6ee6f3d: Reks: To set the RX ODT limit...

Override RX ODT and DRAM geometry for Micron part MT52L256M32D1PF-107.
Use get_ramid() to determine if override is necessary.

Original-Signed-off-by: Kevin Chiu <Kevin.Chiu at quantatw.com>
Original-Reviewed-by: Kane Chen <kane.chen at intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Original-Tested-by: Keith Tzeng <keith.tzeng at quantatw.com>

Change-Id: Iea8c3c67e5afb21285dc15ad665474ad5f192423
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
A src/mainboard/google/cyan/variants/reks/romstage.c
1 file changed, 47 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/22268/1

diff --git a/src/mainboard/google/cyan/variants/reks/romstage.c b/src/mainboard/google/cyan/variants/reks/romstage.c
new file mode 100644
index 0000000..5414cbd
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/reks/romstage.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/romstage.h>
+#include <baseboard/variants.h>
+#include <mainboard/google/cyan/spd/spd_util.h>
+
+void variant_memory_init_params(MEMORY_INIT_UPD *memory_params)
+{
+	int ram_id = get_ramid();
+
+	/*
+	 *  RAMID = A - 4GiB Micron MT52L256M32D1PF-107
+	 *  RAMID = 2 - 2GiB Micron MT52L256M32D1PF-107
+	 */
+	if (ram_id == 2 || ram_id == 0xA) {
+
+		/*
+		 * For new micron part, it requires read/receive
+		 * enable training before sending cmds to get MR8.
+		 * To override dram geometry settings as below:
+		 *
+		 * PcdDramWidth = x32
+		 * PcdDramDensity = 8Gb
+		 * PcdDualRankDram = disable
+		 */
+		memory_params->PcdRxOdtLimitChannel0 = 1;
+		memory_params->PcdRxOdtLimitChannel1 = 1;
+		memory_params->PcdDisableAutoDetectDram = 1;
+		memory_params->PcdDramWidth = 2;
+		memory_params->PcdDramDensity = 3;
+		memory_params->PcdDualRankDram = 0;
+	}
+}

-- 
To view, visit https://review.coreboot.org/22268
To unsubscribe, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iea8c3c67e5afb21285dc15ad665474ad5f192423
Gerrit-Change-Number: 22268
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20171101/dd4b7bc6/attachment-0001.html>