[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: [WIP] Enable common SMI code for APL
Brandon Breitenstein (Code Review)
gerrit at coreboot.org
Wed May 31 23:44:14 CEST 2017
Brandon Breitenstein has uploaded a new change for review. ( https://review.coreboot.org/19393 )
Change subject: soc/intel/apollolake: [WIP] Enable common SMI code for APL
......................................................................
soc/intel/apollolake: [WIP] Enable common SMI code for APL
This update changes Apollolake to use the new common SMI code. This
will help to reduce code duplication and streamline code bring up.
This patch depends on the PMC implementation for common code.
Change-Id: I97a5bce74c6f47fee9966e0442be533291199042
Signed-off-by: Brandon Breitenstein <brandon.breitenstein at intel.com>
---
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/Makefile.inc
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/apollolake/include/soc/pm.h
M src/soc/intel/apollolake/include/soc/smm.h
M src/soc/intel/apollolake/memmap.c
D src/soc/intel/apollolake/smi.c
M src/soc/intel/apollolake/smihandler.c
8 files changed, 25 insertions(+), 103 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/19393/6
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 892412d..f2c72cb 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -62,9 +62,9 @@
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_RTC
select SOC_INTEL_COMMON_BLOCK_SA
+ select SOC_INTEL_COMMON_BLOCK_SMI
select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_LPSS_I2C
- select SOC_INTEL_COMMON_SMI
select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
select UDELAY_TSC
select TSC_CONSTANT_RATE
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 36455f3..dfb6e79 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -68,7 +68,6 @@
ramstage-y += pmutil.c
ramstage-y += pmc.c
ramstage-y += reset.c
-ramstage-y += smi.c
ramstage-y += sram.c
ramstage-y += spi.c
ramstage-y += xdci.c
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index ff300bc..8ea6519 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -25,11 +25,12 @@
#include <cpu/x86/mtrr.h>
#include <device/device.h>
#include <device/pci.h>
+#include <fsp/memmap.h>
+#include <intelblocks/smi.h>
#include <reg_script.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
#include <soc/pm.h>
-#include <soc/smm.h>
#include <cpu/intel/turbo.h>
static const struct reg_script core_msr_script[] = {
@@ -193,9 +194,9 @@
.get_cpu_count = get_cpu_count,
.get_smm_info = get_smm_info,
.get_microcode_info = get_microcode_info,
- .pre_mp_smm_init = southbridge_smm_clear_state,
+ .pre_mp_smm_init = smi_southbridge_clear_state,
.relocation_handler = relocation_handler,
- .post_mp_init = southbridge_smm_enable_smi,
+ .post_mp_init = smi_southbridge_enable,
};
void apollolake_init_cpus(device_t dev)
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index 7bad122..3728fff 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -82,6 +82,8 @@
#define BIOS_EN (1 << SMI_BIOS) /* Assert SMI# on GBL_RLS bit */
#define EOS (1 << SMI_EOS) /* End of SMI (deassert SMI#) */
#define GBL_SMI_EN (1 << SMI_GBL) /* Global SMI Enable */
+/* Save SMI Params for this platform to pass to enable_smi */
+#define ENABLE_SMI_PARAMS (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS | GPIO_EN)
#define SMI_STS 0x44
/* Bits for SMI status */
diff --git a/src/soc/intel/apollolake/include/soc/smm.h b/src/soc/intel/apollolake/include/soc/smm.h
index 740d02b..68e8b77 100644
--- a/src/soc/intel/apollolake/include/soc/smm.h
+++ b/src/soc/intel/apollolake/include/soc/smm.h
@@ -24,6 +24,7 @@
/* These helpers are for performing SMM relocation. */
void southbridge_clear_smi_status(void);
+void southbridge_trigger_smi(void);
/*
* The initialization of the southbridge is split into 2 compoments. One is
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c
index 0f85b10..c40f81c 100644
--- a/src/soc/intel/apollolake/memmap.c
+++ b/src/soc/intel/apollolake/memmap.c
@@ -27,9 +27,10 @@
#include <assert.h>
#include <cbmem.h>
#include <device/pci.h>
+#include <fsp/memmap.h>
+#include <intelblocks/smi.h>
#include <soc/systemagent.h>
#include <soc/pci_devs.h>
-#include <soc/smm.h>
static uintptr_t smm_region_start(void)
{
diff --git a/src/soc/intel/apollolake/smi.c b/src/soc/intel/apollolake/smi.c
deleted file mode 100644
index 227f2f0..0000000
--- a/src/soc/intel/apollolake/smi.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Intel Corp.
- * (Written by Lance Zhao <lijian.zhao at intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <console/console.h>
-#include <arch/io.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/smm.h>
-#include <string.h>
-#include <soc/pm.h>
-#include <soc/smm.h>
-
-void southbridge_smm_clear_state(void)
-{
- printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
-
- if (pmc_get_smi_en() & APMC_EN) {
- printk(BIOS_INFO, "SMI# handler already enabled?\n");
- return;
- }
-
- printk(BIOS_DEBUG, "Done\n");
-
- /* Dump and clear status registers */
- pmc_clear_smi_status();
- pmc_clear_pm1_status();
- pmc_clear_tco_status();
- pmc_clear_gpe_status();
-}
-
-void southbridge_smm_enable_smi(void)
-{
- printk(BIOS_DEBUG, "Enabling SMIs.\n");
- /* Configure events */
- pmc_enable_pm1(PWRBTN_EN | GBL_EN);
- pmc_disable_gpe(PME_B0_EN);
-
- /* Enable SMI generation */
- pmc_enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS | GPIO_EN);
-}
-
-void southbridge_clear_smi_status(void)
-{
- /* Clear SMI status */
- pmc_clear_smi_status();
-
- /* Clear PM1 status */
- pmc_clear_pm1_status();
-
- /* Set EOS bit so other SMIs can occur. */
- pmc_enable_smi(EOS);
-}
-
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
- /*
- * Issue SMI to set the gnvs pointer in SMM.
- * tcg and smi1 are unused.
- *
- * EAX = APM_CNT_GNVS_UPDATE
- * EBX = gnvs pointer
- * EDX = APM_CNT
- */
- asm volatile (
- "outb %%al, %%dx\n\t"
- : /* ignore result */
- : "a" (APM_CNT_GNVS_UPDATE),
- "b" ((u32)gnvs),
- "d" (APM_CNT)
- );
-}
diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c
index 0272a5c..91f100d 100644
--- a/src/soc/intel/apollolake/smihandler.c
+++ b/src/soc/intel/apollolake/smihandler.c
@@ -21,22 +21,27 @@
#include <cpu/x86/smm.h>
#include <device/pci_def.h>
#include <elog.h>
+#include <intelblocks/smi.h>
+#include <intelblocks/smihandler.h>
#include <soc/nvs.h>
#include <soc/pm.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
-#include <soc/intel/common/smi.h>
#include <spi-generic.h>
#include <stdint.h>
#include <stdlib.h>
-#include <soc/smm.h>
-int smm_disable_busmaster(device_t dev)
+int smihandler_disable_busmaster(device_t dev)
{
if (dev == PCH_DEV_PMC)
return 0;
return 1;
+}
+
+uint16_t smihandler_get_acpi_base(void)
+{
+ return ACPI_PMIO_BASE;
}
const struct smm_save_state_ops *get_smm_save_state_ops(void)
@@ -45,24 +50,24 @@
}
void __attribute__((weak))
-mainboard_smi_gpi_handler(const struct gpi_status *sts) { }
+smi_mainboard_gpi_handler(const struct gpi_status *sts) { }
static void southbridge_smi_gpi(const struct smm_save_state_ops *save_state_ops)
{
struct gpi_status smi_sts;
gpi_clear_get_smi_status(&smi_sts);
- mainboard_smi_gpi_handler(&smi_sts);
+ smi_mainboard_gpi_handler(&smi_sts);
/* Clear again after mainboard handler */
gpi_clear_get_smi_status(&smi_sts);
}
const smi_handler_t southbridge_smi[32] = {
- [SLP_SMI_STS] = southbridge_smi_sleep,
- [APM_SMI_STS] = southbridge_smi_apmc,
- [FAKE_PM1_SMI_STS] = southbridge_smi_pm1,
+ [SLP_SMI_STS] = smihandler_southbridge_sleep,
+ [APM_SMI_STS] = smihandler_southbridge_apmc,
+ [FAKE_PM1_SMI_STS] = smihandler_southbridge_pm1,
[GPIO_SMI_STS] = southbridge_smi_gpi,
- [TCO_SMI_STS] = southbridge_smi_tco,
- [PERIODIC_SMI_STS] = southbridge_smi_periodic,
+ [TCO_SMI_STS] = smihandler_southbridge_tco,
+ [PERIODIC_SMI_STS] = smihandler_southbridge_periodic,
};
--
To view, visit https://review.coreboot.org/19393
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I97a5bce74c6f47fee9966e0442be533291199042
Gerrit-PatchSet: 6
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Brenton Dong <brenton.m.dong at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
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