[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Use Intel timer common code

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded a new change for review. ( https://review.coreboot.org/19913 )

Change subject: soc/intel/apollolake: Use Intel timer common code
......................................................................

soc/intel/apollolake: Use Intel timer common code

Change-Id: I7b415711d01ddc0d998eba62de2c2139045efa80
Signed-off-by: Aamir Bohra <aamir.bohra at intel.com>
---
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/Makefile.inc
D src/soc/intel/apollolake/tsc_freq.c
3 files changed, 1 insertion(+), 36 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/19913/1

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 8312611..21b9132 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -63,6 +63,7 @@
 	select SOC_INTEL_COMMON_BLOCK_SA
 	select SOC_INTEL_COMMON_BLOCK_RTC
 	select SOC_INTEL_COMMON_BLOCK_SA
+	select SOC_INTEL_COMMON_BLOCK_TIMER
 	select SOC_INTEL_COMMON_BLOCK_UART
 	select SOC_INTEL_COMMON_BLOCK_XDCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 33bc7cf..a2768e7 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -18,7 +18,6 @@
 bootblock-y += mmap_boot.c
 bootblock-y += pmutil.c
 bootblock-y += spi.c
-bootblock-y += tsc_freq.c
 bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
 bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S
 
@@ -32,7 +31,6 @@
 romstage-y += memmap.c
 romstage-y += meminit.c
 romstage-y += mmap_boot.c
-romstage-y += tsc_freq.c
 romstage-y += pmutil.c
 romstage-y += reset.c
 romstage-y += spi.c
@@ -42,7 +40,6 @@
 smm-y += gpio.c
 smm-y += smihandler.c
 smm-y += spi.c
-smm-y += tsc_freq.c
 smm-y += uart_early.c
 
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
@@ -65,7 +62,6 @@
 ramstage-y += nhlt.c
 ramstage-y += northbridge.c
 ramstage-y += spi.c
-ramstage-y += tsc_freq.c
 ramstage-y += pmutil.c
 ramstage-y += pmc.c
 ramstage-y += reset.c
@@ -79,7 +75,6 @@
 postcar-y += mmap_boot.c
 postcar-y += spi.c
 postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
-postcar-y += tsc_freq.c
 
 postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
 
@@ -89,7 +84,6 @@
 verstage-y += memmap.c
 verstage-y += mmap_boot.c
 verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
-verstage-y += tsc_freq.c
 verstage-y += pmutil.c
 verstage-y += reset.c
 verstage-y += spi.c
diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c
deleted file mode 100644
index db456bf..0000000
--- a/src/soc/intel/apollolake/tsc_freq.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <cpu/intel/speedstep.h>
-#include <cpu/intel/turbo.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/tsc.h>
-#include <soc/cpu.h>
-#include <console/console.h>
-#include <delay.h>
-#include "chip.h"
-
-unsigned long tsc_freq_mhz(void)
-{
-	msr_t msr = rdmsr(MSR_PLATFORM_INFO);
-	return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff));
-}
\ No newline at end of file

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I7b415711d01ddc0d998eba62de2c2139045efa80
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>