[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Use Intel timer common code
Aamir Bohra (Code Review)
gerrit at coreboot.org
Wed May 31 20:52:16 CEST 2017
Aamir Bohra has uploaded a new change for review. ( https://review.coreboot.org/19912 )
Change subject: soc/intel/skylake: Use Intel timer common code
......................................................................
soc/intel/skylake: Use Intel timer common code
Use timer code from soc/intel/common. This code removes
monotonic timer refrence w.r.t MSR 24Mhz counter(0x637)
and use tsc timer.
Change-Id: I7fad620b11c9e5db128f646639c79ea58a0a574f
Signed-off-by: Aamir Bohra <aamir.bohra at intel.com>
---
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/Makefile.inc
D src/soc/intel/skylake/monotonic_timer.c
D src/soc/intel/skylake/tsc_freq.c
4 files changed, 3 insertions(+), 81 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/19912/4
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index c36a4a7..affb81d 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -63,6 +63,7 @@
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SATA
select SOC_INTEL_COMMON_BLOCK_SMBUS
+ select SOC_INTEL_COMMON_BLOCK_TIMER
select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_BLOCK_XHCI
select SOC_INTEL_COMMON_NHLT
@@ -73,6 +74,7 @@
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_CONSTANT_RATE
+ select TSC_MONOTONIC_TIMER
select TSC_SYNC_MFENCE
select UDELAY_TSC
select ACPI_NHLT
@@ -160,7 +162,7 @@
default 0x400000
config MONOTONIC_TIMER_MSR
- def_bool y
+ def_bool n
select HAVE_MONOTONIC_TIMER
help
Provide a monotonic timer using the 24MHz MSR counter.
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 1ea5287..29a89d3 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -18,33 +18,27 @@
bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c
bootblock-y += gpio.c
bootblock-y += gspi.c
-bootblock-y += monotonic_timer.c
bootblock-y += pch.c
bootblock-y += pmutil.c
bootblock-y += spi.c
-bootblock-y += tsc_freq.c
verstage-y += gspi.c
-verstage-y += monotonic_timer.c
verstage-y += pch.c
verstage-$(CONFIG_UART_DEBUG) += uart_debug.c
verstage-y += pmutil.c
verstage-y += i2c.c
verstage-y += spi.c
-verstage-y += tsc_freq.c
romstage-y += gpio.c
romstage-y += gspi.c
romstage-y += i2c.c
romstage-y += memmap.c
-romstage-y += monotonic_timer.c
romstage-y += me.c
romstage-y += pch.c
romstage-y += pei_data.c
romstage-y += pmutil.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
romstage-y += spi.c
-romstage-y += tsc_freq.c
romstage-$(CONFIG_UART_DEBUG) += uart_debug.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
@@ -62,7 +56,6 @@
ramstage-y += lpc.c
ramstage-y += me.c
ramstage-y += memmap.c
-ramstage-y += monotonic_timer.c
ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += opregion.c
ramstage-y += pch.c
ramstage-y += pei_data.c
@@ -74,23 +67,18 @@
ramstage-y += smi.c
ramstage-y += spi.c
ramstage-y += systemagent.c
-ramstage-y += tsc_freq.c
ramstage-y += uart.c
ramstage-$(CONFIG_UART_DEBUG) += uart_debug.c
ramstage-y += vr_config.c
smm-y += gpio.c
-smm-y += monotonic_timer.c
smm-y += pch.c
smm-y += pmutil.c
smm-y += smihandler.c
smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
-smm-y += tsc_freq.c
smm-$(CONFIG_UART_DEBUG) += uart_debug.c
postcar-y += memmap.c
-postcar-y += monotonic_timer.c
-postcar-y += tsc_freq.c
postcar-$(CONFIG_UART_DEBUG) += uart_debug.c
# cpu_microcode_bins += ???
diff --git a/src/soc/intel/skylake/monotonic_timer.c b/src/soc/intel/skylake/monotonic_timer.c
deleted file mode 100644
index 7e33223..0000000
--- a/src/soc/intel/skylake/monotonic_timer.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <cpu/x86/msr.h>
-#include <timer.h>
-#include <soc/msr.h>
-
-static inline uint32_t read_counter_msr(void)
-{
- /*
- * Even though the MSR is 64-bit it is assumed that the hardware
- * is polled frequently enough to only use the lower 32-bits.
- */
- msr_t counter_msr;
-
- counter_msr = rdmsr(MSR_COUNTER_24_MHZ);
-
- return counter_msr.lo;
-}
-
-void timer_monotonic_get(struct mono_time *mt)
-{
- /* Always increases. Don't normalize to 0 between stages. */
- mono_time_set_usecs(mt, read_counter_msr() / 24);
-}
diff --git a/src/soc/intel/skylake/tsc_freq.c b/src/soc/intel/skylake/tsc_freq.c
deleted file mode 100644
index 7654e83..0000000
--- a/src/soc/intel/skylake/tsc_freq.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/tsc.h>
-#include <intelblocks/cpu.h>
-#include <soc/msr.h>
-
-unsigned long tsc_freq_mhz(void)
-{
- msr_t platform_info;
-
- platform_info = rdmsr(MSR_PLATFORM_INFO);
- return CPU_BCLK * ((platform_info.lo >> 8) & 0xff);
-}
--
To view, visit https://review.coreboot.org/19912
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I7fad620b11c9e5db128f646639c79ea58a0a574f
Gerrit-PatchSet: 4
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma at intel.com>
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