[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block/gpio: Port gpio code from Apollolake ...
Hannah Williams (Code Review)
gerrit at coreboot.org
Wed May 31 20:20:21 CEST 2017
Hannah Williams has posted comments on this change. ( https://review.coreboot.org/19759 )
Change subject: soc/intel/common/block/gpio: Port gpio code from Apollolake to common
......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/#/c/19759/14/src/soc/intel/common/block/gpio/gpio.c
File src/soc/intel/common/block/gpio/gpio.c:
PS14, Line 132:
: config_offset = pad_config_offset(comm, cfg->pad);
: pad_conf0 = pcr_read32(comm->port, config_offset);
: pad_conf1 = pcr_read32(comm->port, config_offset + GPIO_DWx_SIZE(1));
: if (IS_ENABLED(CONFIG_DEBUG_SOC_COMMON_BLOCK_GPIO))
: printk(BIOS_DEBUG,
: "gpio_padcfg [0x%02x, %d] DW0 [0x%08x : 0x%08x] "
: "DW1 [0x%08x : 0x%08x]\n",
: comm->port,
: (cfg->pad - comm->first_pad),
: pad_conf0,/* old value */
: cfg->pad_config0, /* new value */
: pad_conf1,/* old value */
: cfg->pad_config1); /* new value */
:
: pad_conf0 &= ~PAD_DW0_MASK;
: pcr_write32(comm->port, config_offset, pad_conf0 |
: (cfg->pad_config0 & PAD_DW0_MASK));
: pad_conf1 &= ~PAD_DW1_MASK;
: pcr_write32(comm->port, config_offset + GPIO_DWx_SIZE(1),
: pad_conf1 | (cfg->pad_config1 & PAD_DW1_MASK));
Shall I change this logic to only configure what comes in from the gpio table and remove PAD_DW0_MASK and PAD_DW1_MASK? Basically it would be to move to existing APL code
--
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Gerrit-MessageType: comment
Gerrit-Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa
Gerrit-PatchSet: 14
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