[coreboot-gerrit] Change in coreboot[master]: arch/arm/armv7: Correct checkpatch errors
Logan Carlson (Code Review)
gerrit at coreboot.org
Wed May 31 20:03:58 CEST 2017
Logan Carlson has uploaded a new change for review. ( https://review.coreboot.org/19996 )
Change subject: arch/arm/armv7: Correct checkpatch errors
......................................................................
arch/arm/armv7: Correct checkpatch errors
- Correct whitespace issues with files under arch/arm/armv7.
- Fix comments and remove unnecessary line continuations in mmu.c
Change-Id: I69d50030b07b1919555feca44967472922176a81
Signed-off-by: Logan Carlson <logancarlson at google.com>
---
M src/arch/arm/armv7/cache.c
M src/arch/arm/armv7/mmu.c
M src/arch/arm/armv7/thread.c
3 files changed, 13 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/19996/1
diff --git a/src/arch/arm/armv7/cache.c b/src/arch/arm/armv7/cache.c
index eea514b..ef3ad01 100644
--- a/src/arch/arm/armv7/cache.c
+++ b/src/arch/arm/armv7/cache.c
@@ -84,7 +84,7 @@
dsb();
while ((void *)line < addr + len) {
- switch(op) {
+ switch (op) {
case OP_DCCIMVAC:
dccimvac(line);
break;
diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c
index 4123bb4..20cb12f 100644
--- a/src/arch/arm/armv7/mmu.c
+++ b/src/arch/arm/armv7/mmu.c
@@ -43,14 +43,14 @@
/* See B3.6.2 of ARMv7 Architecture Reference Manual */
/* TODO: Utilize the contiguous hint flag */
#define ATTR_BLOCK (\
- 0ULL << 54 | /* XN. 0:Not restricted */ \
- 0ULL << 53 | /* PXN. 0:Not restricted */ \
- 1 << 10 | /* AF. 1:Accessed. This is to prevent access \
- * fault when accessed for the first time */ \
- 0 << 6 | /* AP[2:1]. 0b00:full access from PL1 */ \
- 0 << 5 | /* NS. 0:Output address is in Secure space */ \
- 0 << 1 | /* block/table. 0:block entry */ \
- 1 << 0 /* validity. 1:valid */ \
+ 0ULL << 54 | /* XN. 0:Not restricted */
+ 0ULL << 53 | /* PXN. 0:Not restricted */
+ 1 << 10 | /* AF. 1:Accessed. This is to prevent access
+ * fault when accessed for the first time */
+ 0 << 6 | /* AP[2:1]. 0b00:full access from PL1 */
+ 0 << 5 | /* NS. 0:Output address is in Secure space */
+ 0 << 1 | /* block/table. 0:block entry */
+ 1 << 0 /* validity. 1:valid */
)
#define ATTR_PAGE (ATTR_BLOCK | 1 << 1)
#define ATTR_NEXTLEVEL (0x3)
@@ -280,12 +280,12 @@
table[0] = ATTR_UNUSED;
if (CONFIG_ARM_LPAE) {
- pte_t *const pgd_buff = (pte_t*)(_ttb + 16*KiB);
+ pte_t *const pgd_buff = (pte_t *)(_ttb + 16*KiB);
pte_t *pmd = ttb_buff;
int i;
printk(BIOS_DEBUG, "LPAE Translation tables are @ %p\n",
- ttb_buff);
+ ttb_buff);
ASSERT((read_mmfr0() & 0xf) >= 5);
/*
@@ -308,7 +308,7 @@
*/
for (i = 0; i < 4; i++) {
pgd_buff[i] = ((uint32_t)pmd & NEXTLEVEL_MASK) |
- ATTR_NEXTLEVEL;
+ ATTR_NEXTLEVEL;
pmd += BLOCK_SIZE / PAGE_SIZE;
}
diff --git a/src/arch/arm/armv7/thread.c b/src/arch/arm/armv7/thread.c
index a3b1d0c..3b8d1af 100644
--- a/src/arch/arm/armv7/thread.c
+++ b/src/arch/arm/armv7/thread.c
@@ -39,7 +39,7 @@
}
void arch_prepare_thread(struct thread *t,
- void asmlinkage (*thread_entry)(void *), void *arg)
+ void asmlinkage(*thread_entry)(void *), void *arg)
{
uintptr_t stack = t->stack_current;
int i;
--
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I69d50030b07b1919555feca44967472922176a81
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Logan Carlson <logancarlson at google.com>
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