[coreboot-gerrit] Change in coreboot[master]: mb/lenovo/t430: Fix PCIe hot-plug ports

[Patrick Rudolph (Code Review)]

Patrick Rudolph has submitted this change and it was merged. ( https://review.coreboot.org/19928 )

Change subject: mb/lenovo/t430: Fix PCIe hot-plug ports
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mb/lenovo/t430: Fix PCIe hot-plug ports

Port 0 is connected to SD-card reader.
Don't mark it as hot-plugable.

Change-Id: I5d3d4c7541683a6c09aac47ca251a6dad23ad1ab
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
Reviewed-on: https://review.coreboot.org/19928
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/mainboard/lenovo/t430/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Arthur Heymans: Looks good to me, approved
  build bot (Jenkins): Verified



diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb
index 86c8756..0a121b7 100644
--- a/src/mainboard/lenovo/t430/devicetree.cb
+++ b/src/mainboard/lenovo/t430/devicetree.cb
@@ -47,7 +47,7 @@
 			register "gpi13_routing" = "2"
 			register "gpi1_routing" = "2"
 			register "p_cnt_throttling_supported" = "1"
-			register "pcie_hotplug_map" = "{ 1, 0, 1, 0, 0, 0, 0, 0 }"
+			register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
 			register "pcie_port_coalesce" = "1"
 			register "sata_interface_speed_support" = "0x3"
 			register "sata_port_map" = "0x17"

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Gerrit-MessageType: merged
Gerrit-Change-Id: I5d3d4c7541683a6c09aac47ca251a6dad23ad1ab
Gerrit-PatchSet: 3
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Patrick Rudolph <siro at das-labor.org>
Gerrit-Reviewer: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-Reviewer: Patrick Rudolph <siro at das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>