[coreboot-gerrit] Change in coreboot[master]: vendorcode/intel/skykabylake: change gpio RXEVCFG default to...

[Kane Chen (Code Review)]

Kane Chen has uploaded a new change for review. ( https://review.coreboot.org/19992 )

Change subject: vendorcode/intel/skykabylake: change gpio RXEVCFG default to edge
......................................................................

vendorcode/intel/skykabylake: change gpio RXEVCFG default to edge

The original gpio macro sets GPI or native pin RXEVCFG to LEVEL trigger.
This would cause unused interrupts happen while OS is trying to enable
GPIO interrupt and set RXEVCFG to edge trigger.

BUG=b:62067569
TEST=checked unused interrupt on SD_CD dose not happen after s3 resume

Change-Id: I42b9cd80b494e24c55b97e54cdf59bfd24dd9054
Signed-off-by: Kane Chen <kane.chen at intel.com>
---
M src/soc/intel/skylake/include/soc/gpio.h
1 file changed, 5 insertions(+), 5 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/19992/1

diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h
index ae534cd..1129c45 100644
--- a/src/soc/intel/skylake/include/soc/gpio.h
+++ b/src/soc/intel/skylake/include/soc/gpio.h
@@ -110,24 +110,24 @@
 /* Native Function - No Rx buffer manipulation */
 #define PAD_CFG_NF(pad_, term_, rst_, func_) \
 	_PAD_CFG(pad_, term_, \
-	_DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, func_, NO, NO))
+	_DW0_VALS(rst_, RAW, NO, EDGE, NO, NO, NO, NO, NO, NO, func_, NO, NO))
 
 /* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S. */
 #define PAD_CFG_NF_1V8(pad_, term_, rst_, func_) \
 	_PAD_CFG_ATTRS(pad_, term_, \
-	_DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, \
+	_DW0_VALS(rst_, RAW, NO, EDGE, NO, NO, \
 		NO, NO, NO, NO, func_, NO, NO), PAD_FIELD(PAD_TOL, 1V8))
 
 /* Unused PINS will be controlled by GPIO controller (PMODE = GPIO) and
    GPIO TX/RX will be disabled. */
 #define PAD_CFG_NC(pad_) \
 	_PAD_CFG(pad_, NONE, \
-	_DW0_VALS(DEEP, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, YES, YES))
+	_DW0_VALS(DEEP, RAW, NO, EDGE, NO, NO, NO, NO, NO, NO, GPIO, YES, YES))
 
 /* General purpose output with termination. */
 #define PAD_CFG_TERM_GPO(pad_, val_, term_, rst_) \
 	_PAD_CFG(pad_, term_, \
-	_DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, YES, NO) \
+	_DW0_VALS(rst_, RAW, NO, EDGE, NO, NO, NO, NO, NO, NO, GPIO, YES, NO) \
 		| PAD_FIELD_VAL(GPIOTXSTATE, val_))
 
 /* General purpose output. By default no termination. */
@@ -137,7 +137,7 @@
 /* General purpose input with no special IRQ routing. */
 #define PAD_CFG_GPI(pad_, term_, rst_) \
 	_PAD_CFG_ATTRS(pad_, term_, \
-	_DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, NO, YES),\
+	_DW0_VALS(rst_, RAW, NO, EDGE, NO, NO, NO, NO, NO, NO, GPIO, NO, YES),\
 	PAD_FIELD(HOSTSW, GPIO))
 
 /* General purpose input passed through to IOxAPIC. Assume APIC logic can

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I42b9cd80b494e24c55b97e54cdf59bfd24dd9054
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Kane Chen <kane.chen at intel.com>