[coreboot-gerrit] Change in coreboot[master]: soc: Add AMD Stoney Ridge southbridge code

[Marc Jones (Code Review)]

Marc Jones has posted comments on this change. ( https://review.coreboot.org/19722 )

Change subject: soc: Add AMD Stoney Ridge southbridge code
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Patch Set 4:

created the following issues to track problems found in review:
Kahlee: coreboot - stoneyridge - check uart index bounds	62201567
Kahlee: coreboot - stoneyridge - use device macros	62200746
Kahlee: coreboot -stoneyridge - fix lpc.c	62200877
Kahlee: coreboot -- stoneyridge - fix and find the correct location for amd_pci_int_types.h	62200834
Kahlee: coreboot - stoneyridge - find the correct location for amd_pci_int_defs.h	62200907
Kahlee: coreboot -stoneyridge - fix guarded code	62200858
Kahlee: coreboot - stoneyridge - clean up hudson.c	62200891
Kahlee: coreboot - stoneyridge - rename hudson.c and hudson.h	62200157
Kahlee: coreboot - stoneyridge - cleanup sd.c	62200312
Kahlee: coreboot - stoneyridge - fix sata.c	62200375
Kahlee: coreboot - clean up stoneyridge smbus files	62200225
Kahlee: coreboot - cleanup magic southbridge registers	62199625
Kahlee: coreboot soc cleanup - remove unused and non NULL function pointers and empty functions	62199225

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Gerrit-MessageType: comment
Gerrit-Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b
Gerrit-PatchSet: 4
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Marc Jones <marc at marcjonesconsulting.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki at gmail.com>
Gerrit-Reviewer: Marc Jones <marc at marcjonesconsulting.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd at gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-HasComments: No