[coreboot-gerrit] Change in coreboot[master]: cpu/amd/car: Fix checkpatch warnings
Evelyn Huang (Code Review)
gerrit at coreboot.org
Wed May 31 00:13:33 CEST 2017
Evelyn Huang has uploaded a new change for review. ( https://review.coreboot.org/19988 )
Change subject: cpu/amd/car: Fix checkpatch warnings
......................................................................
cpu/amd/car: Fix checkpatch warnings
Fix line over 80 characters warnings and space after function name
warning.
Change-Id: Id5a5abaa06f8e285ff58436789318cb9cd3b7ac3
Signed-off-by: Evelyn Huang <evhuang at google.com>
---
M src/cpu/amd/car/disable_cache_as_ram.c
M src/cpu/amd/car/post_cache_as_ram.c
2 files changed, 30 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/19988/1
diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c
index bab464e..efc9118 100644
--- a/src/cpu/amd/car/disable_cache_as_ram.c
+++ b/src/cpu/amd/car/disable_cache_as_ram.c
@@ -4,7 +4,8 @@
* original idea yhlu 6.2005 (assembler code)
*
* Copyright (C) 2010 Rudolf Marek <r.marek at assembler.cz>
- * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>, Raptor Engineering
+ * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>,
+ * Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -31,7 +32,8 @@
return family;
}
-static inline __attribute__((always_inline)) void disable_cache_as_ram(uint8_t skip_sharedc_config)
+static inline __attribute__((always_inline))
+void disable_cache_as_ram(uint8_t skip_sharedc_config)
{
msr_t msr;
uint32_t family;
@@ -52,12 +54,17 @@
#if CONFIG_DCACHE_RAM_SIZE > 0x18000
wrmsr(MTRR_FIX_4K_D8000, msr);
#endif
- /* disable fixed mtrr from now on, it will be enabled by ramstage again */
+ /* disable fixed mtrr from now on,
+ * it will be enabled by ramstage again
+ */
msr = rdmsr(SYSCFG_MSR);
- msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn);
+ msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn
+ | SYSCFG_MSR_MtrrFixDramModEn);
wrmsr(SYSCFG_MSR, msr);
- /* Set the default memory type and disable fixed and enable variable MTRRs */
+ /* Set the default memory type and
+ * disable fixed and enable variable MTRRs
+ */
msr.hi = 0;
msr.lo = (1 << 11);
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index efcd111..064222a 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -48,20 +48,23 @@
static void memcpy_(void *d, const void *s, size_t len)
{
print_car_debug(" Copy [%08x-%08x] to [%08x - %08x] ...",
- (uint32_t) s, (uint32_t) (s + len - 1), (uint32_t) d, (uint32_t) (d + len - 1));
+ (uint32_t) s, (uint32_t) (s + len - 1),
+ (uint32_t) d, (uint32_t) (d + len - 1));
memcpy(d, s, len);
}
static void memset_(void *d, int val, size_t len)
{
- print_car_debug(" Fill [%08x-%08x] ...", (uint32_t) d, (uint32_t) (d + len - 1));
+ print_car_debug(" Fill [%08x-%08x] ...",
+ (uint32_t) d, (uint32_t) (d + len - 1));
memset(d, val, len);
}
static int memcmp_(void *d, const void *s, size_t len)
{
print_car_debug(" Compare [%08x-%08x] with [%08x - %08x] ...",
- (uint32_t) s, (uint32_t) (s + len - 1), (uint32_t) d, (uint32_t) (d + len - 1));
+ (uint32_t) s, (uint32_t) (s + len - 1),
+ (uint32_t) d, (uint32_t) (d + len - 1));
return memcmp(d, s, len);
}
@@ -71,10 +74,13 @@
print_car_debug("Prepare CAR migration and stack regions...");
if (s3resume) {
- void *resume_backup_memory = acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
+ void *resume_backup_memory =
+ acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
if (resume_backup_memory)
- memcpy_(resume_backup_memory + HIGH_MEMORY_SAVE - backup_top,
- (void *)(CONFIG_RAMTOP - backup_top), backup_top);
+ memcpy_(resume_backup_memory
+ + HIGH_MEMORY_SAVE - backup_top,
+ (void *)(CONFIG_RAMTOP - backup_top),
+ backup_top);
}
memset_((void *)(CONFIG_RAMTOP - backup_top), 0, backup_top);
@@ -87,7 +93,8 @@
print_car_debug("Prepare ramstage memory region...");
if (s3resume) {
- void *resume_backup_memory = acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
+ void *resume_backup_memory =
+ acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
if (resume_backup_memory)
memcpy_(resume_backup_memory, (void *) CONFIG_RAMBASE,
HIGH_MEMORY_SAVE - backup_top);
@@ -118,7 +125,9 @@
* boundary during romstage execution
*/
volatile uint32_t *lower_stack_boundary;
- lower_stack_boundary = (void *)((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - CONFIG_DCACHE_BSP_STACK_SIZE);
+ lower_stack_boundary =
+ (void *)((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)
+ - CONFIG_DCACHE_BSP_STACK_SIZE);
if ((*lower_stack_boundary) != 0xdeadbeef)
printk(BIOS_WARNING, "BSP overran lower stack boundary. Undefined behaviour may result!\n");
@@ -159,7 +168,7 @@
/* We do not come back. */
}
-void cache_as_ram_new_stack (void)
+void cache_as_ram_new_stack(void)
{
print_car_debug("Disabling cache as RAM now\n");
disable_cache_as_ram_bsp();
--
To view, visit https://review.coreboot.org/19988
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Id5a5abaa06f8e285ff58436789318cb9cd3b7ac3
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Evelyn Huang <evhuang at google.com>
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