[coreboot-gerrit] Change in coreboot[master]: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM

[Martin Roth (Code Review)]

Martin Roth has posted comments on this change. ( https://review.coreboot.org/19960 )

Change subject: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM
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Patch Set 1:

(4 comments)

https://review.coreboot.org/#/c/19960/1/src/northbridge/intel/sandybridge/raminit_mrc.c
File src/northbridge/intel/sandybridge/raminit_mrc.c:

PS1, Line 308: 0x5e04
MC_BIOS_DATA in northbridge/intel/sandybridge/raminit_common.h?

I guess none of the other MCHBAR values are defined anywhere, so maybe that doesn't make sense.


PS1, Line 310: addr_decode_ch
This looks like channels, but we can have two dimms per channel, so should this be multiplied by 2, or should we have a j loop?


PS1, Line 325: 122
Hrm - looks like we need an spd_ddr3.h file.


PS1, Line 328: same for all modules so use first
what if not all modules are populated?


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Gerrit-MessageType: comment
Gerrit-Change-Id: I13d784a17eda01ccc9569c4562bba6d14af5157d
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude at gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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