[coreboot-gerrit] Change in coreboot[master]: soc/broadwell: add ACPI method to generate USB port info

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19969 )

Change subject: soc/broadwell: add ACPI method to generate USB port info
......................................................................

soc/broadwell: add ACPI method to generate USB port info

Add ACPI method GPLD to generate port location data when
passed visiblity info.  Will be used by _PLD method in
board-specific USB .asl files.

Change-Id: Id6e6699fe3eaafbe6847479d45c70a1d57bd327a
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/soc/intel/broadwell/acpi/xhci.asl
1 file changed, 16 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/19969/1

diff --git a/src/soc/intel/broadwell/acpi/xhci.asl b/src/soc/intel/broadwell/acpi/xhci.asl
index bbf9878..53ef127 100644
--- a/src/soc/intel/broadwell/acpi/xhci.asl
+++ b/src/soc/intel/broadwell/acpi/xhci.asl
@@ -355,6 +355,22 @@
 	{
 		Name (_ADR, 0x00000000)
 
+		// GPLD: Generate Port Location Data (PLD)
+		Method (GPLD, 1, Serialized) {
+			Name (PCKG, Package (0x01) {
+				Buffer (0x10) {}
+			})
+
+			// REV: Revision 0x02 for ACPI 5.0
+			CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV)
+			Store (0x02, REV)
+
+			// VISI: Port visibility to user per port
+			CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI)
+			Store (Arg0, VISI)
+			Return (PCKG)
+		}
+
 		// How many are there?
 		Device (PRT1) { Name (_ADR, 1) } // USB Port 0
 		Device (PRT2) { Name (_ADR, 2) } // USB Port 1

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Id6e6699fe3eaafbe6847479d45c70a1d57bd327a
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>