[coreboot-gerrit] Change in coreboot[master]: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19960 )

Change subject: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM
......................................................................

nb/sandybridge:add CBMEM_MEMINFO table when initing RAM

Populate a memory_info struct with PEI and SPD data,
in order to inject the CBMEM_INFO table necessary to
populate a type17 SMBIOS table.

On Broadwell, this is done by the MRC binary, but the older
SandyBridge MRC binary doesn't populate the pei_data struct
with all the info needed, so we have to pull it from the SPD.

Some values are hardcoded  based on platform specifications.

Change-Id: I13d784a17eda01ccc9569c4562bba6d14af5157d
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/northbridge/intel/sandybridge/raminit.h
M src/northbridge/intel/sandybridge/raminit_mrc.c
2 files changed, 52 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/19960/1

diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h
index 4e684ec..9066b7f 100644
--- a/src/northbridge/intel/sandybridge/raminit.h
+++ b/src/northbridge/intel/sandybridge/raminit.h
@@ -29,5 +29,6 @@
 void save_mrc_data(struct pei_data *pei_data);
 void mainboard_fill_pei_data(struct pei_data *pei_data);
 int fixup_sandybridge_errata(void);
+void setup_sdram_meminfo(struct pei_data *pei_data);
 
 #endif				/* RAMINIT_H */
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 09d82d6..77c947b 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -31,6 +31,7 @@
 #include "pei_data.h"
 #include "sandybridge.h"
 #include <vboot/vboot_common.h>
+#include <memory_info.h>
 
 /* Management Engine is in the southbridge */
 #include "southbridge/intel/bd82x6x/me.h"
@@ -284,4 +285,54 @@
 		outb(0x6, 0xcf9);
 		halt();
 	}
+	setup_sdram_meminfo(&pei_data);
+}
+
+void setup_sdram_meminfo(struct pei_data *pei_data)
+{
+	u32 addr_decoder_common, addr_decode_ch[2];
+	struct memory_info* mem_info;
+	struct dimm_info *dimm;
+	int ddr_frequency;
+	int dimm_size;
+	int i;
+	int dimm_cnt = 0;
+
+	mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info));
+	memset(mem_info, 0, sizeof(struct memory_info));
+
+	addr_decoder_common = MCHBAR32(0x5000);
+	addr_decode_ch[0] = MCHBAR32(0x5004);
+	addr_decode_ch[1] = MCHBAR32(0x5008);
+
+	ddr_frequency = (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100;
+
+	for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
+		u32 ch_conf = addr_decode_ch[i];
+		dimm_size = ((ch_conf >> 0) & 0xff) * 256;
+
+		if (dimm_size) {
+			dimm_cnt++;
+			dimm = &mem_info->dimm[i];
+			dimm->dimm_size = dimm_size;
+			dimm->ddr_type = 3;				// DRAM
+			dimm->ddr_frequency = ddr_frequency;
+			dimm->rank_per_dimm = 1;
+			dimm->channel_num = i;
+			dimm->dimm_num = 0;
+			dimm->bank_locator = i * 2;
+			memcpy(dimm->serial, 				// bytes 122-125 in SPD
+				&pei_data->spd_data[i][122],		// same for all modules so use first
+				sizeof(uint8_t) * 4);			// since known good
+			memcpy(dimm->module_part_number,		// bytes 128-145 in SPD
+				&pei_data->spd_data[0][128],		// same for all modules so use first
+				sizeof(uint8_t) * 18);			// since known good
+			dimm->mod_id =
+				(pei_data->spd_data[0][118] << 8) | 	// bytes 117/118 (LSB/MSB)
+				(pei_data->spd_data[0][117] & 0xFF);
+			dimm->mod_type = 3;				//SPD_SODIMM
+			dimm->bus_width = 0x3;				//64-bit
+		}
+	}
+	mem_info->dimm_cnt = dimm_cnt;
 }

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I13d784a17eda01ccc9569c4562bba6d14af5157d
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>