[coreboot-gerrit] Change in coreboot[master]: lib/spd_bin: make SMBus SPD addresses an input

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19915 )

Change subject: lib/spd_bin: make SMBus SPD addresses an input
......................................................................


lib/spd_bin: make SMBus SPD addresses an input

Instead of assuming the mapping of dimm number to SPD SMBus address,
allow the mainboard to provide its own mapping. That way, global
resources of empty SPD contents aren't wasted in order to address
a dimm on a mainboard that doesn't meet the current assumption.

Change-Id: Id0e79231dc2303373badaae003038a1ac06a5635
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-on: https://review.coreboot.org/19915
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Furquan Shaikh <furquan at google.com>
Reviewed-by: Naresh Solanki <naresh.solanki at intel.com>
---
M src/include/spd_bin.h
M src/lib/spd_bin.c
M src/mainboard/google/fizz/romstage.c
M src/mainboard/intel/kblrvp/romstage.c
4 files changed, 8 insertions(+), 3 deletions(-)

Approvals:
  Naresh Solanki: Looks good to me, approved
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved



diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h
index 4d5ce2f..3783faf 100644
--- a/src/include/spd_bin.h
+++ b/src/include/spd_bin.h
@@ -43,6 +43,7 @@
 #define LPDDR4_SPD_PART_LEN	20
 
 struct spd_block {
+	u8 addr_map[CONFIG_DIMM_MAX];
 	u8 *spd_array[CONFIG_DIMM_MAX];
 	/* Length of each dimm */
 	u16 len;
diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c
index 5c4f09f..3e26004 100644
--- a/src/lib/spd_bin.c
+++ b/src/lib/spd_bin.c
@@ -159,7 +159,7 @@
 
 	for (i = 0 ; i < CONFIG_DIMM_MAX; i++) {
 		get_spd(spd_data_ptr + i * CONFIG_DIMM_SPD_SIZE,
-			0xA0 + (i << 1));
+			blk->addr_map[i]);
 		blk->spd_array[i] = spd_data_ptr + i * CONFIG_DIMM_SPD_SIZE;
 	}
 
diff --git a/src/mainboard/google/fizz/romstage.c b/src/mainboard/google/fizz/romstage.c
index be1d552..4c816df 100644
--- a/src/mainboard/google/fizz/romstage.c
+++ b/src/mainboard/google/fizz/romstage.c
@@ -31,7 +31,9 @@
 	memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target));
 
 	/* Read spd block to get memory config */
-	struct spd_block blk;
+	struct spd_block blk = {
+		.addr_map = { 0xa0, 0xa4, },
+	};
 	mem_cfg->DqPinsInterleaved = 1;
 	get_spd_smbus(&blk);
 	mem_cfg->MemorySpdDataLen = blk.len;
diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c
index a3b1ba1..9082254 100644
--- a/src/mainboard/intel/kblrvp/romstage.c
+++ b/src/mainboard/intel/kblrvp/romstage.c
@@ -50,7 +50,9 @@
 		/* Memory leak is ok since we have memory mapped boot media */
 		mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev);
 	} else {  /* for CONFIG_BOARD_INTEL_KBLRVP7 */
-		struct spd_block blk;
+		struct spd_block blk = {
+			.addr_map = { 0xa0, 0xa2, 0xa4, 0xa6, },
+		};
 
 		mem_cfg->DqPinsInterleaved = 1;
 		get_spd_smbus(&blk);

-- 
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Gerrit-MessageType: merged
Gerrit-Change-Id: Id0e79231dc2303373badaae003038a1ac06a5635
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Kane Chen <kane.chen at intel.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Naresh Solanki <naresh.solanki at intel.com>
Gerrit-Reviewer: Shelley Chen <shchen at google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>