[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Use common gpio for apollolake
Hannah Williams (Code Review)
gerrit at coreboot.org
Sat May 27 05:02:10 CEST 2017
Hannah Williams has uploaded a new change for review. ( https://review.coreboot.org/19949 )
Change subject: soc/intel/apollolake: Use common gpio for apollolake
......................................................................
soc/intel/apollolake: Use common gpio for apollolake
Change-Id: I0fcc22df5eaec014f3b89755415f051b05aa554a
Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/Makefile.inc
R src/soc/intel/apollolake/acpi/gpio_apl.asl
M src/soc/intel/apollolake/acpi/gpiolib.asl
M src/soc/intel/apollolake/acpi/southbridge.asl
M src/soc/intel/apollolake/chip.h
D src/soc/intel/apollolake/gpio.c
A src/soc/intel/apollolake/gpio_apl.c
M src/soc/intel/apollolake/include/soc/gpio.h
R src/soc/intel/apollolake/include/soc/gpio_apl.h
10 files changed, 152 insertions(+), 683 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/19949/1
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 56f0d20..a5c02e8 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -322,4 +322,12 @@
string
default "aplk"
+config SOC_INTEL_COMMON_BLOCK_GPIO
+ def_bool y
+ select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG
+
+config GPIO_NUM_PAD_CFG_REGS
+ int
+ default 2
+
endif
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 9b1f440..c95cc41 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -11,7 +11,7 @@
bootblock-y += bootblock/bootblock.c
bootblock-y += bootblock/bootblock.c
bootblock-y += car.c
-bootblock-y += gpio.c
+bootblock-y += gpio_apl.c
bootblock-y += heci.c
bootblock-y += i2c.c
bootblock-y += lpc_lib.c
@@ -24,7 +24,7 @@
romstage-y += car.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
-romstage-y += gpio.c
+romstage-y += gpio_apl.c
romstage-y += heci.c
romstage-y += i2c.c
romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
@@ -39,7 +39,7 @@
smm-y += mmap_boot.c
smm-y += pmutil.c
-smm-y += gpio.c
+smm-y += gpio_apl.c
smm-y += smihandler.c
smm-y += spi.c
smm-y += tsc_freq.c
@@ -51,7 +51,7 @@
ramstage-y += cse.c
ramstage-y += elog.c
ramstage-y += dsp.c
-ramstage-y += gpio.c
+ramstage-y += gpio_apl.c
ramstage-y += graphics.c
ramstage-y += heci.c
ramstage-y += i2c.c
diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio_apl.asl
similarity index 99%
rename from src/soc/intel/apollolake/acpi/gpio.asl
rename to src/soc/intel/apollolake/acpi/gpio_apl.asl
index ceba72b..db667a3 100644
--- a/src/soc/intel/apollolake/acpi/gpio.asl
+++ b/src/soc/intel/apollolake/acpi/gpio_apl.asl
@@ -14,7 +14,7 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-#include <soc/gpio_defs.h>
+#include <soc/gpio_apl.h>
#include <soc/pcr_ids.h>
#include "gpiolib.asl"
@@ -200,3 +200,4 @@
*/
Method(_L0F, 0) {}
}
+
diff --git a/src/soc/intel/apollolake/acpi/gpiolib.asl b/src/soc/intel/apollolake/acpi/gpiolib.asl
index a4d4b00..3e99f09 100644
--- a/src/soc/intel/apollolake/acpi/gpiolib.asl
+++ b/src/soc/intel/apollolake/acpi/gpiolib.asl
@@ -81,7 +81,7 @@
Method (CHSA, 0x1, Serialized)
{
/* Arg0 - GPIO pad offset relative to the community */
- Add (HOSTSW_OWN_REG_BASE, Multiply (Divide (Arg0, 32), 4), Local1)
+ Add (HOSTSW_OWN_REG_0, Multiply (Divide (Arg0, 32), 4), Local1)
Return (Local1)
}
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index 823173f..5a172a3 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -37,7 +37,7 @@
#include "pci_irqs.asl"
/* GPIO controller */
-#include "gpio.asl"
+#include "gpio_apl.asl"
#include "xhci.asl"
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index bf25009..93bb5a1 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -19,7 +19,6 @@
#define _SOC_APOLLOLAKE_CHIP_H_
#include <soc/gpe.h>
-#include <soc/gpio_defs.h>
#include <soc/gpio.h>
#include <intelblocks/lpss_i2c.h>
#include <device/i2c.h>
diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c
deleted file mode 100644
index c237506..0000000
--- a/src/soc/intel/apollolake/gpio.c
+++ /dev/null
@@ -1,421 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corp.
- * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <assert.h>
-#include <gpio.h>
-#include <intelblocks/itss.h>
-#include <intelblocks/pcr.h>
-#include <soc/gpio.h>
-#include <soc/pcr_ids.h>
-#include <soc/pm.h>
-
-/* This list must be in order, from highest pad numbers, to lowest pad numbers*/
-static const struct pad_community {
- uint16_t first_pad;
- uint8_t port;
- uint8_t num_gpi_regs;
- uint8_t gpi_offset;
- const char *grp_name;
-} gpio_communities[] = {
- {
- .port = PID_GPIO_SW,
- .first_pad = SW_OFFSET,
- .num_gpi_regs = NUM_SW_GPI_REGS,
- .gpi_offset = 0,
- .grp_name = "GPIO_GPE_SW",
- }, {
- .port = PID_GPIO_W,
- .first_pad = W_OFFSET,
- .num_gpi_regs = NUM_W_GPI_REGS,
- .gpi_offset = NUM_SW_GPI_REGS,
- .grp_name = "GPIO_GPE_W",
- }, {
- .port = PID_GPIO_NW,
- .first_pad = NW_OFFSET,
- .num_gpi_regs = NUM_NW_GPI_REGS,
- .gpi_offset = NUM_W_GPI_REGS + NUM_SW_GPI_REGS,
- .grp_name = "GPIO_GPE_NW",
- }, {
- .port = PID_GPIO_N,
- .first_pad = N_OFFSET,
- .num_gpi_regs = NUM_N_GPI_REGS,
- .gpi_offset = NUM_NW_GPI_REGS + NUM_W_GPI_REGS
- + NUM_SW_GPI_REGS,
- .grp_name = "GPIO_GPE_N",
- }
-};
-
-static const struct pad_community *gpio_get_community(uint16_t pad)
-{
- const struct pad_community *map = gpio_communities;
-
- assert(pad < TOTAL_PADS);
-
- while (map->first_pad > pad)
- map++;
-
- return map;
-}
-
-static void gpio_configure_itss(const struct pad_config *cfg,
- uint16_t port, uint16_t pad_cfg_offset)
-{
- /* No ITSS configuration in SMM. */
- if (ENV_SMM)
- return;
-
- int irq;
-
- /* Set up ITSS polarity if pad is routed to APIC.
- *
- * The ITSS takes only active high interrupt signals. Therefore,
- * if the pad configuration indicates an inversion assume the
- * intent is for the ITSS polarity. Before forwarding on the
- * request to the APIC there's an inversion setting for how the
- * signal is forwarded to the APIC. Honor the inversion setting
- * in the GPIO pad configuration so that a hardware active low
- * signal looks that way to the APIC (double inversion).
- */
- if (!(cfg->config0 & PAD_CFG0_ROUTE_IOAPIC))
- return;
-
- irq = pcr_read32(port, pad_cfg_offset + sizeof(uint32_t));
- irq &= PAD_CFG1_IRQ_MASK;
- if (!irq) {
- printk(BIOS_ERR, "GPIO %u doesn't support APIC routing,\n",
- cfg->pad);
- return;
- }
-
- itss_set_irq_polarity(irq, !!(cfg->config0 & PAD_CFG0_RX_POL_INVERT));
-}
-
-static void gpio_configure_owner(const struct pad_config *cfg,
- uint16_t port, int pin)
-{
- uint16_t hostsw_reg;
-
- /* The 4th bit in pad_config 1 (RO) is used to indicate if the pad
- * needs GPIO driver ownership.
- */
- if (!(cfg->config1 & PAD_CFG1_GPIO_DRIVER))
- return;
-
- /* Based on the gpio pin number configure the corresponding bit in
- * HOSTSW_OWN register. Value of 0x1 indicates GPIO Driver onwership.
- */
- hostsw_reg = HOSTSW_OWN_REG_BASE + ((pin / 32) * sizeof(uint32_t));
- pcr_or32(port, hostsw_reg, (1 << (pin % 32)));
-}
-
-static void gpi_enable_smi(const struct pad_config *cfg, uint16_t port, int pin)
-{
- uint32_t value;
- uint16_t sts_reg;
- uint16_t en_reg;
- int group;
-
- if (((cfg->config0) & PAD_CFG0_ROUTE_SMI) != PAD_CFG0_ROUTE_SMI)
- return;
-
- group = pin / GPIO_MAX_NUM_PER_GROUP;
-
- sts_reg = GPI_SMI_STS_OFFSET(group);
- value = pcr_read32(port, sts_reg);
- /* Write back 1 to reset the sts bits */
- pcr_write32(port, sts_reg, value);
-
- /* Set enable bits */
- en_reg = GPI_SMI_EN_OFFSET(group);
- pcr_or32(port, en_reg, (1 << (pin % GPIO_MAX_NUM_PER_GROUP)));
-}
-
-void gpio_configure_pad(const struct pad_config *cfg)
-{
- uint32_t dw1;
- const struct pad_community *comm = gpio_get_community(cfg->pad);
- uint16_t config_offset = PAD_CFG_OFFSET(cfg->pad - comm->first_pad);
-
- /* Iostandby bits are tentatively stored in [3:0] bits (RO) of config1.
- * dw1 is used to extract the bits of Iostandby.
- * This is done to preserve config1 size as unit16 in gpio.h.
- */
- dw1 = cfg->config1 & ~PAD_CFG1_IOSSTATE_MASK;
- dw1 |= (cfg->config1 & PAD_CFG1_IOSSTATE_MASK)
- << PAD_CFG1_IOSSTATE_SHIFT;
-
- pcr_write32(comm->port, config_offset, cfg->config0);
- pcr_write32(comm->port, config_offset + sizeof(uint32_t), dw1);
-
- gpio_configure_itss(cfg, comm->port, config_offset);
- gpio_configure_owner(cfg, comm->port, cfg->pad - comm->first_pad);
-
- gpi_enable_smi(cfg, comm->port, cfg->pad - comm->first_pad);
-}
-
-void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads)
-{
- uint32_t i;
-
- for (i = 0; i < num_pads; i++)
- gpio_configure_pad(cfg + i);
-}
-
-void *gpio_dwx_address(const uint16_t pad)
-{
- /* Calculate Address of DW0 register for given GPIO
- * pad - GPIO number
- * returns - address of GPIO
- */
- const struct pad_community *comm = gpio_get_community(pad);
- return pcr_reg_address(comm->port,
- PAD_CFG_OFFSET(pad - comm->first_pad));
-}
-
-uint8_t gpio_get_pad_portid(const uint16_t pad)
-{
- /* Get the port id of given pad
- * pad - GPIO number
- * returns - given pad port id
- */
- const struct pad_community *comm = gpio_get_community(pad);
- return comm->port;
-}
-
-void gpio_input_pulldown(gpio_t gpio)
-{
- struct pad_config cfg = PAD_CFG_GPI(gpio, DN_20K, DEEP);
- gpio_configure_pad(&cfg);
-}
-
-void gpio_input_pullup(gpio_t gpio)
-{
- struct pad_config cfg = PAD_CFG_GPI(gpio, UP_20K, DEEP);
- gpio_configure_pad(&cfg);
-}
-
-void gpio_input(gpio_t gpio)
-{
- struct pad_config cfg = PAD_CFG_GPI(gpio, NONE, DEEP);
- gpio_configure_pad(&cfg);
-}
-
-void gpio_output(gpio_t gpio, int value)
-{
- struct pad_config cfg = PAD_CFG_GPO(gpio, value, DEEP);
- gpio_configure_pad(&cfg);
-}
-
-int gpio_get(gpio_t gpio_num)
-{
- uint32_t reg;
- const struct pad_community *comm = gpio_get_community(gpio_num);
- uint16_t config_offset = PAD_CFG_OFFSET(gpio_num - comm->first_pad);
-
- reg = pcr_read32(comm->port, config_offset);
-
- return !!(reg & PAD_CFG0_RX_STATE);
-}
-
-void gpio_set(gpio_t gpio_num, int value)
-{
- const struct pad_community *comm = gpio_get_community(gpio_num);
- uint16_t config_offset = PAD_CFG_OFFSET(gpio_num - comm->first_pad);
-
- pcr_rmw32(comm->port, config_offset,
- ~PAD_CFG0_TX_STATE, (!!value & PAD_CFG0_TX_STATE));
-}
-
-const char *gpio_acpi_path(gpio_t gpio_num)
-{
- const struct pad_community *comm = gpio_get_community(gpio_num);
-
- switch (comm->port) {
- case PID_GPIO_N:
- return "\\_SB.GPO0";
- case PID_GPIO_NW:
- return "\\_SB.GPO1";
- case PID_GPIO_W:
- return "\\_SB.GPO2";
- case PID_GPIO_SW:
- return "\\_SB.GPO3";
- }
-
- return NULL;
-}
-
-uint16_t gpio_acpi_pin(gpio_t gpio_num)
-{
- const struct pad_community *comm = gpio_get_community(gpio_num);
-
- switch (comm->port) {
- case PID_GPIO_N:
- return PAD_N(gpio_num);
- case PID_GPIO_NW:
- return PAD_NW(gpio_num);
- case PID_GPIO_W:
- return PAD_W(gpio_num);
- case PID_GPIO_SW:
- return PAD_SW(gpio_num);
- }
-
- return gpio_num;
-}
-
-static void print_gpi_status(const struct gpi_status *sts)
-{
- int i;
- int group;
- int index = 0;
- int bit_set;
- int num_groups;
- int abs_bit;
- const struct pad_community *comm;
-
- for (i = 0; i < ARRAY_SIZE(gpio_communities); i++) {
- comm = &gpio_communities[i];
- num_groups = comm->num_gpi_regs;
- index = comm->gpi_offset;
- for (group = 0; group < num_groups; group++, index++) {
- for (bit_set = 31; bit_set >= 0; bit_set--) {
- if (!(sts->grp[index] & (1 << bit_set)))
- continue;
-
- abs_bit = bit_set;
- abs_bit += group * GPIO_MAX_NUM_PER_GROUP;
- printk(BIOS_DEBUG, "%s %d\n", comm->grp_name,
- abs_bit);
- }
- }
- }
-}
-
-void gpi_clear_get_smi_status(struct gpi_status *sts)
-{
- int i;
- int group;
- int index = 0;
- uint32_t sts_value;
- uint32_t en_value;
- int num_groups;
- const struct pad_community *comm;
-
- for (i = 0; i < ARRAY_SIZE(gpio_communities); i++) {
- comm = &gpio_communities[i];
- num_groups = comm->num_gpi_regs;
- index = comm->gpi_offset;
- for (group = 0; group < num_groups; group++, index++) {
- sts_value = pcr_read32(gpio_communities[i].port,
- GPI_SMI_STS_OFFSET(group));
- en_value = pcr_read32(gpio_communities[i].port,
- GPI_SMI_EN_OFFSET(group));
- sts->grp[index] = sts_value & en_value;
- /* Clear the set status bits. */
- pcr_write32(gpio_communities[i].port,
- GPI_SMI_STS_OFFSET(group), sts->grp[index]);
- }
- }
-
- if (IS_ENABLED(CONFIG_DEBUG_SMI))
- print_gpi_status(sts);
-
-}
-
-int gpi_status_get(const struct gpi_status *sts, gpio_t gpi)
-{
- uint8_t sts_index;
- const struct pad_community *comm = gpio_get_community(gpi);
-
- /* Check if valid gpi */
- if (comm == NULL)
- return 0;
-
- sts_index = comm->gpi_offset + ((gpi - comm->first_pad) /
- GPIO_MAX_NUM_PER_GROUP);
-
- return !!(sts->grp[sts_index] & (1 << (gpi % GPIO_MAX_NUM_PER_GROUP)));
-}
-
-/* Helper function to map PMC register groups to tier1 sci groups */
-static int pmc_gpe_route_to_gpio(int route)
-{
- switch (route) {
- case PMC_GPE_SW_31_0:
- return GPIO_GPE_SW_31_0;
- case PMC_GPE_SW_63_32:
- return GPIO_GPE_SW_63_32;
- case PMC_GPE_NW_31_0:
- return GPIO_GPE_NW_31_0;
- case PMC_GPE_NW_63_32:
- return GPIO_GPE_NW_63_32;
- case PMC_GPE_NW_95_64:
- return GPIO_GPE_NW_95_64;
- case PMC_GPE_N_31_0:
- return GPIO_GPE_N_31_0;
- case PMC_GPE_N_63_32:
- return GPIO_GPE_N_63_32;
- case PMC_GPE_W_31_0:
- return GPIO_GPE_W_31_0;
- default:
- return -1;
- }
-}
-
-void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d)
-{
- int i;
- uint32_t misccfg_mask;
- uint32_t misccfg_value;
- int ret;
-
- /* Get the group here for community specific MISCCFG register.
- * If any of these returns -1 then there is some error in devicetree
- * where the group is probably hardcoded and does not comply with the
- * PMC group defines. So we return from here and MISCFG is set to
- * default.
- */
- ret = pmc_gpe_route_to_gpio(gpe0b);
- if (ret == -1)
- return;
- gpe0b = ret;
-
- ret = pmc_gpe_route_to_gpio(gpe0c);
- if (ret == -1)
- return;
- gpe0c = ret;
-
- ret = pmc_gpe_route_to_gpio(gpe0d);
- if (ret == -1)
- return;
- gpe0d = ret;
-
- misccfg_value = gpe0b << MISCCFG_GPE0_DW0_SHIFT;
- misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT;
- misccfg_value |= gpe0d << MISCCFG_GPE0_DW2_SHIFT;
-
- /* Program GPIO_MISCCFG */
- misccfg_mask = ~(MISCCFG_GPE0_DW2_MASK |
- MISCCFG_GPE0_DW1_MASK |
- MISCCFG_GPE0_DW0_MASK);
-
- for (i = 0; i < ARRAY_SIZE(gpio_communities); i++) {
- const struct pad_community *comm = &gpio_communities[i];
-
- pcr_rmw32(comm->port, GPIO_MISCCFG,
- misccfg_mask, misccfg_value);
- }
-}
diff --git a/src/soc/intel/apollolake/gpio_apl.c b/src/soc/intel/apollolake/gpio_apl.c
new file mode 100644
index 0000000..8b3819b
--- /dev/null
+++ b/src/soc/intel/apollolake/gpio_apl.c
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <gpio.h>
+#include <intelblocks/gpio.h>
+#include <intelblocks/pcr.h>
+#include <soc/pm.h>
+
+const struct pad_community apl_gpio_communities[] = {
+ {
+ .port = PID_GPIO_SW,
+ .first_pad = SW_OFFSET,
+ .last_pad = LPC_FRAMEB,
+ .num_gpi_regs = NUM_SW_GPI_REGS,
+ .gpi_offset = 0,
+ .name = "GPIO_GPE_SW",
+ .acpi_path = "\\_SB.GPO3",
+ }, {
+ .port = PID_GPIO_W,
+ .first_pad = W_OFFSET,
+ .last_pad = SUSPWRDNACK,
+ .num_gpi_regs = NUM_W_GPI_REGS,
+ .gpi_offset = NUM_SW_GPI_REGS,
+ .name = "GPIO_GPE_W",
+ .acpi_path = "\\_SB.GPO2",
+ }, {
+ .port = PID_GPIO_NW,
+ .first_pad = NW_OFFSET,
+ .last_pad = GPIO_123,
+ .num_gpi_regs = NUM_NW_GPI_REGS,
+ .gpi_offset = NUM_W_GPI_REGS + NUM_SW_GPI_REGS,
+ .name = "GPIO_GPE_NW",
+ .acpi_path = "\\_SB.GPO1",
+ }, {
+ .port = PID_GPIO_N,
+ .first_pad = N_OFFSET,
+ .last_pad = SVID0_CLK,
+ .num_gpi_regs = NUM_N_GPI_REGS,
+ .gpi_offset = NUM_NW_GPI_REGS + NUM_W_GPI_REGS
+ + NUM_SW_GPI_REGS,
+ .name = "GPIO_GPE_N",
+ .acpi_path = "\\_SB.GPO0",
+ }
+};
+
+const struct pad_community *soc_gpio_get_community(size_t
+ *num_communities)
+{
+ *num_communities = ARRAY_SIZE(apl_gpio_communities);
+ return apl_gpio_communities;
+}
+
+/* Helper function to map PMC register groups to tier1 sci groups */
+int soc_gpe_route_to_gpio(int route)
+{
+ switch (route) {
+ case PMC_GPE_SW_31_0:
+ return GPIO_GPE_SW_31_0;
+ case PMC_GPE_SW_63_32:
+ return GPIO_GPE_SW_63_32;
+ case PMC_GPE_NW_31_0:
+ return GPIO_GPE_NW_31_0;
+ case PMC_GPE_NW_63_32:
+ return GPIO_GPE_NW_63_32;
+ case PMC_GPE_NW_95_64:
+ return GPIO_GPE_NW_95_64;
+ case PMC_GPE_N_31_0:
+ return GPIO_GPE_N_31_0;
+ case PMC_GPE_N_63_32:
+ return GPIO_GPE_N_63_32;
+ case PMC_GPE_W_31_0:
+ return GPIO_GPE_W_31_0;
+ default:
+ return -1;
+ }
+}
diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h
index 85fc759..67ae495 100644
--- a/src/soc/intel/apollolake/include/soc/gpio.h
+++ b/src/soc/intel/apollolake/include/soc/gpio.h
@@ -1,8 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Intel Corp.
- * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ * Copyright (C) 2017 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -15,170 +14,9 @@
* GNU General Public License for more details.
*/
-#ifndef _SOC_APOLLOLAKE_GPIO_H_
-#define _SOC_APOLLOLAKE_GPIO_H_
+#ifndef _SOC_APL_GPIO_H_
+#define _SOC_APL_GPIO_H_
-#include <soc/gpio_defs.h>
-/* __ACPI__ guard is needed to ignore below code in ACPI/ASL compilation */
-#ifndef __ACPI__
-#include <types.h>
+#include <soc/gpio_apl.h>
-typedef uint32_t gpio_t;
-
-/*
- * Structure to represent GPI status for GPE and SMI. Use helper
- * functions for interrogating particular GPIs. Here the number of
- * array elements is total number of groups that can be present in all
- * the communities.
- */
-struct gpi_status {
- uint32_t grp[NUM_GPI_STATUS_REGS];
-};
-
-/*
- * Clear GPI SMI status and fill in the structure representing enabled
- * and set status.
- */
-void gpi_clear_get_smi_status(struct gpi_status *sts);
-
-/* Return 1 if gpio is set in the gpi_status struct. Otherwise 0. */
-int gpi_status_get(const struct gpi_status *sts, gpio_t gpi);
-
-#define PAD_FUNC(value) PAD_CFG0_MODE_##value
-#define PAD_RESET(value) PAD_CFG0_RESET_##value
-#define PAD_PULL(value) PAD_CFG1_PULL_##value
-#define PAD_IOSSTATE(value) PAD_CFG1_IOSSTATE_##value
-#define PAD_IOSTERM(value) PAD_CFG1_IOSTERM_##value
-#define PAD_IRQ_CFG(route, trig, inv) \
- (PAD_CFG0_ROUTE_##route | \
- PAD_CFG0_TRIG_##trig | \
- (PAD_CFG0_RX_POL_##inv))
-
-#define _PAD_CFG_STRUCT(__pad, __config0, __config1) \
- { \
- .pad = __pad, \
- .config0 = __config0, \
- .config1 = __config1, \
- }
-
-/* Native function configuration */
-#define PAD_CFG_NF(pad, pull, rst, func) \
- PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, TxLASTRxE)
-
-/* Native function configuration for standby state */
-#define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \
- PAD_CFG_NF_IOSSTATE_IOSTERM(pad,pull, rst, func, iosstate, SAME)
-
-#define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \
- _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
- PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
-
-/* General purpose output, no pullup/down. */
-#define PAD_CFG_GPO(pad, val, rst) \
- _PAD_CFG_STRUCT(pad, \
- PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \
- PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE))
-
-/* General purpose input */
-#define PAD_CFG_GPI(pad, pull, rst) \
- _PAD_CFG_STRUCT(pad, \
- PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
- PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE))
-
-/* General purpose input. The following macro sets the
- * Host Software Pad Ownership to GPIO Driver mode.
- */
-#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \
- _PAD_CFG_STRUCT(pad, \
- PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
- PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxLASTRxE))
-
-/* No Connect configuration for unused pad.
- * NC should be GPI with Term as PU20K, PD20K, NONE depending upon default Term
- */
-#define PAD_NC(pad, pull) PAD_CFG_GPI(pad, pull, DEEP)
-
-/* General purpose input, routed to APIC */
-#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \
- _PAD_CFG_STRUCT(pad, \
- PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
- PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \
- PAD_IOSSTATE(TxLASTRxE))
-
-/*
- * The following APIC macros assume the APIC will handle the filtering
- * on its own end. One just needs to pass an active high message into the
- * ITSS.
- */
-#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \
- PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, INVERT)
-
-#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \
- PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE)
-
-/* General purpose input, routed to SMI */
-#define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \
- _PAD_CFG_STRUCT(pad, \
- PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
- PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \
- PAD_IOSSTATE(TxLASTRxE))
-
-#define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \
- PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT)
-
-#define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \
- PAD_CFG_GPI_SMI(pad, pull, rst, trig, NONE)
-
-/* General purpose input, routed to SCI */
-#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \
- _PAD_CFG_STRUCT(pad, \
- PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
- PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
- PAD_IOSSTATE(TxLASTRxE))
-
-#define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \
- PAD_CFG_GPI_SCI(pad, pull, rst, trig, INVERT)
-
-#define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \
- PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE)
-
-/* General purpose input, routed to NMI */
-#define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \
- _PAD_CFG_STRUCT(pad, \
- PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
- PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \
- PAD_IOSSTATE(TxLASTRxE))
-
-struct pad_config {
- uint32_t config0;
- uint16_t config1;
- uint16_t pad;
-};
-
-/*
- * Configuration for raw pads. Some pads are designated as only special function
- * pins, and don't have an associated GPIO number, so we need to expose the raw
- * pad configuration functionality.
- */
-void gpio_configure_pad(const struct pad_config *cfg);
-void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads);
-
-/* Calculate GPIO DW0 address */
-void *gpio_dwx_address(const uint16_t pad);
-
-/* Get the port id of given pad */
-uint8_t gpio_get_pad_portid(const uint16_t pad);
-
-/*
- * Set the GPIO groups for the GPE blocks. The values from PMC register GPE_CFG
- * are passed which is then mapped to proper groups for MISCCFG. This basically
- * sets the MISCCFG register bits:
- * dw0 = gpe0_route[11:8]. This is ACPI GPE0b.
- * dw1 = gpe0_route[15:12]. This is ACPI GPE0c.
- * dw2 = gpe0_route[19:16]. This is ACPI GPE0d.
- */
-void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d);
-
-#endif /* __ACPI__ */
-
-#endif /* _SOC_APOLLOLAKE_GPIO_H_ */
+#endif
diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_apl.h
similarity index 76%
rename from src/soc/intel/apollolake/include/soc/gpio_defs.h
rename to src/soc/intel/apollolake/include/soc/gpio_apl.h
index 938d414..f8b6c86 100644
--- a/src/soc/intel/apollolake/include/soc/gpio_defs.h
+++ b/src/soc/intel/apollolake/include/soc/gpio_apl.h
@@ -6,7 +6,7 @@
*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2015 - 2017 Intel Corp.
* (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
@@ -20,8 +20,32 @@
* GNU General Public License for more details.
*/
-#ifndef _SOC_APOLLOLAKE_GPIO_DEFS_H_
-#define _SOC_APOLLOLAKE_GPIO_DEFS_H_
+#ifndef _SOC_APOLLOLAKE_GPIO_H_
+#define _SOC_APOLLOLAKE_GPIO_H_
+
+#include <soc/pcr_ids.h>
+#include <intelblocks/gpio.h>
+
+#define PAD_DW0_MASK (PAD_CFG0_TX_STATE | \
+ PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE | PAD_CFG0_MODE_MASK |\
+ PAD_CFG0_ROUTE_MASK | PAD_CFG0_RXTENCFG_MASK | \
+ PAD_CFG0_RXINV_MASK | PAD_CFG0_PREGFRXSEL | \
+ PAD_CFG0_TRIG_MASK | PAD_CFG0_RXRAW1_MASK | \
+ PAD_CFG0_RXPADSTSEL_MASK | PAD_CFG0_RESET_MASK)
+
+#define PAD_DW1_MASK (PAD_CFG1_IOSTERM_MASK | \
+ PAD_CFG1_PULL_MASK | \
+ PAD_CFG1_IOSSTATE_MASK)
+
+/* number of bits defining the mode */
+#define PAD_MODE_MASK 0x7
+
+/* IOSF port numbers for GPIO comminuties*/
+#define GPIO_SW 0xc0
+#define GPIO_S 0xc2
+#define GPIO_NW 0xc4
+#define GPIO_N 0xc5
+#define GPIO_W 0xc7
/*
* Miscellaneous Configuration register(MISCCFG).These are community specific
@@ -40,98 +64,18 @@
#define GPIO_MAX_NUM_PER_GROUP 32
-#define MISCCFG_GPE0_DW0_SHIFT 8
-#define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW0_SHIFT)
-#define MISCCFG_GPE0_DW1_SHIFT 12
-#define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
-#define MISCCFG_GPE0_DW2_SHIFT 16
-#define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT)
/* Host Software Pad Ownership Register.
* The pins in the community are divided into 3 groups :
* GPIO 0 ~ 31, GPIO 32 ~ 63, GPIO 64 ~ 95
*/
-#define HOSTSW_OWN_REG_BASE 0x80
+#define HOSTSW_OWN_REG_0 0x80
-#define PAD_CFG0_TX_STATE (1 << 0)
-#define PAD_CFG0_RX_STATE (1 << 1)
-#define PAD_CFG0_TX_DISABLE (1 << 8)
-#define PAD_CFG0_RX_DISABLE (1 << 9)
-#define PAD_CFG0_MODE_MASK (7 << 10)
-#define PAD_CFG0_MODE_GPIO (0 << 10)
-#define PAD_CFG0_MODE_FUNC(x) ((x) << 10)
-#define PAD_CFG0_MODE_NF1 (1 << 10)
-#define PAD_CFG0_MODE_NF2 (2 << 10)
-#define PAD_CFG0_MODE_NF3 (3 << 10)
-#define PAD_CFG0_MODE_NF4 (4 << 10)
-#define PAD_CFG0_MODE_NF5 (5 << 10)
-#define PAD_CFG0_ROUTE_NMI (1 << 17)
-#define PAD_CFG0_ROUTE_SMI (1 << 18)
-#define PAD_CFG0_ROUTE_SCI (1 << 19)
-#define PAD_CFG0_ROUTE_IOAPIC (1 << 20)
-#define PAD_CFG0_RX_POL_INVERT (1 << 23)
-#define PAD_CFG0_RX_POL_NONE (0 << 23)
-
-#define PAD_CFG0_TRIG_MASK (3 << 25)
-#define PAD_CFG0_TRIG_LEVEL (0 << 25)
-#define PAD_CFG0_TRIG_EDGE_SINGLE (1 << 25) /* controlled by RX_INVERT*/
-#define PAD_CFG0_TRIG_OFF (2 << 25)
-#define PAD_CFG0_TRIG_EDGE_BOTH (3 << 25)
-#define PAD_CFG0_RESET_MASK (3 << 30)
-#define PAD_CFG0_RESET_PWROK (0 << 30)
-#define PAD_CFG0_RESET_DEEP (1 << 30)
-#define PAD_CFG0_RESET_PLTRST (2 << 30)
-#define PAD_CFG0_RESET_RSMRST (3 << 30)
-
-/* Use the fourth bit in IntSel field to indicate gpio
- * ownership. This field is RO and hence not used during
- * gpio configuration.
- */
-#define PAD_CFG1_GPIO_DRIVER (0x1 << 4)
-#define PAD_CFG1_IRQ_MASK (0xff << 0)
-#define PAD_CFG1_PULL_MASK (0xf << 10)
-#define PAD_CFG1_PULL_NONE (0x0 << 10)
-#define PAD_CFG1_PULL_DN_5K (0x2 << 10)
-#define PAD_CFG1_PULL_DN_20K (0x4 << 10)
-#define PAD_CFG1_PULL_UP_1K (0x9 << 10)
-#define PAD_CFG1_PULL_UP_5K (0xa << 10)
-#define PAD_CFG1_PULL_UP_2K (0xb << 10)
-#define PAD_CFG1_PULL_UP_20K (0xc << 10)
-#define PAD_CFG1_PULL_UP_667 (0xd << 10)
-#define PAD_CFG1_PULL_NATIVE (0xf << 10)
-/* Tx enabled driving last value driven, Rx enabled */
-#define PAD_CFG1_IOSSTATE_TxLASTRxE (0x0 << 0)
-/* Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller
- * internally */
-#define PAD_CFG1_IOSSTATE_Tx0RxDCRx0 (0x1 << 0)
-/* Tx enabled driving 0, Rx disabled and Rx driving 1 back to its controller
- * internally */
-#define PAD_CFG1_IOSSTATE_Tx0RXDCRx1 (0x2 << 0)
-/* Tx enabled driving 1, Rx disabled and Rx driving 0 back to its controller
- * internally */
-#define PAD_CFG1_IOSSTATE_Tx1RXDCRx0 (0x3 << 0)
-/* Tx enabled driving 1, Rx disabled and Rx driving 1 back to its controller
- * internally */
-#define PAD_CFG1_IOSSTATE_Tx1RxDCRx1 (0x4 << 0)
-/* Tx enabled driving 0, Rx enabled */
-#define PAD_CFG1_IOSSTATE_Tx0RxE (0x5 << 0)
-/* Tx enabled driving 1, Rx enabled */
-#define PAD_CFG1_IOSSTATE_Tx1RxE (0x6 << 0)
-/* Hi-Z, Rx driving 0 back to its controller internally */
-#define PAD_CFG1_IOSSTATE_HIZCRx0 (0x7 << 0)
-/* Hi-Z, Rx driving 1 back to its controller internally */
-#define PAD_CFG1_IOSSTATE_HIZCRx1 (0x8 << 0)
-#define PAD_CFG1_IOSSTATE_TxDRxE (0x9 << 0) /* Tx disabled, Rx enabled */
-#define PAD_CFG1_IOSSTATE_IGNORE (0xf << 0) /* Ignore Iostandby */
-#define PAD_CFG1_IOSSTATE_MASK 0xf /* mask to extract Iostandby bits */
-#define PAD_CFG1_IOSSTATE_SHIFT 14 /* set Iostandby bits [17:14] */
-#define PAD_CFG1_IOSTERM_SAME (0x0 << 8) /* Same as functional mode */
-#define PAD_CFG1_IOSTERM_DISPUPD (0x1 << 8) /* Disable Pull-up/Pull-down */
-#define PAD_CFG1_IOSTERM_ENPD (0x2 << 8) /* Enable Pull-down */
-#define PAD_CFG1_IOSTERM_ENPU (0x3 << 8) /* Enable Pull-up */
#define PAD_CFG_BASE 0x500
#define PAD_CFG_OFFSET(pad) (PAD_CFG_BASE + ((pad) * 8))
+
+#define GPI_INT_EN_0 0x110
#define GPI_SMI_STS_0 0x140
#define GPI_SMI_EN_0 0x150
@@ -554,4 +498,13 @@
#define GPIO_72_IRQ 0x65
#define GPIO_73_IRQ 0x66
-#endif /* _SOC_APOLLOLAKE_GPIO_DEFS_H_ */
+#define PAD_CFG_BASE 0x500
+
+
+#ifndef __ACPI__
+struct gpi_status {
+ uint32_t grp[NUM_GPI_STATUS_REGS];
+};
+
+#endif /* __ACPI__ */
+#endif /* _SOC_APOLLOLAKE_GPIO_H_ */
--
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