[coreboot-gerrit] Change in coreboot[master]: mb/google/eve: Update thermal tuning parameters

[Duncan Laurie (Code Review)]

Duncan Laurie has uploaded a new change for review. ( https://review.coreboot.org/19947 )

Change subject: mb/google/eve: Update thermal tuning parameters
......................................................................

mb/google/eve: Update thermal tuning parameters

Modify the DPTF configuration on Eve to relax the severe throttling that
is currently applied and allow performance testing to see better results.

BUG=b:35581264
TEST=performance tests show better results and thermal tests still pass.

Change-Id: I0838f4ec3026bc8bac814698043fa97cf6772cb4
Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
M src/mainboard/google/eve/acpi/dptf.asl
M src/mainboard/google/eve/devicetree.cb
2 files changed, 13 insertions(+), 13 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/19947/1

diff --git a/src/mainboard/google/eve/acpi/dptf.asl b/src/mainboard/google/eve/acpi/dptf.asl
index eaacb46..8937ee9 100644
--- a/src/mainboard/google/eve/acpi/dptf.asl
+++ b/src/mainboard/google/eve/acpi/dptf.asl
@@ -29,12 +29,12 @@
 
 #define DPTF_TSR2_SENSOR_ID	3
 #define DPTF_TSR2_SENSOR_NAME	"DRAM"
-#define DPTF_TSR2_PASSIVE	55
+#define DPTF_TSR2_PASSIVE	65
 #define DPTF_TSR2_CRITICAL	75
 
 #define DPTF_TSR3_SENSOR_ID	4
 #define DPTF_TSR3_SENSOR_NAME	"eMMC"
-#define DPTF_TSR3_PASSIVE	55
+#define DPTF_TSR3_PASSIVE	65
 #define DPTF_TSR3_CRITICAL	75
 
 #undef DPTF_ENABLE_FAN_CONTROL
@@ -56,19 +56,19 @@
 	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
 
 	/* CPU Effect on Charger */
-	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 50, 600, 0, 0, 0, 0 },
 
 	/* CPU Effect on DRAM */
-	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 90, 0, 0, 0, 0 },
+	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
 
 	/* CPU Effect on eMMC */
-	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 },
+	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 50, 600, 0, 0, 0, 0 },
 
 	/* Charger Throttle Effect on Charger (TSR1) */
 	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
 
 	/* Charger Throttle Effect on eMMC (TSR3) */
-	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR3, 200, 600, 0, 0, 0, 0 },
+	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 },
 })
 
 Name (MPPC, Package ()
@@ -77,15 +77,15 @@
 	Package () {	/* Power Limit 1 */
 		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
 		2500,	/* PowerLimitMinimum */
-		4500,	/* PowerLimitMaximum */
-		1000,	/* TimeWindowMinimum */
-		1000,	/* TimeWindowMaximum */
-		250	/* StepSize */
+		7000,	/* PowerLimitMaximum */
+		5000,	/* TimeWindowMinimum */
+		5000,	/* TimeWindowMaximum */
+		200	/* StepSize */
 	},
 	Package () {	/* Power Limit 2 */
 		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
-		7000,	/* PowerLimitMinimum */
-		7000,	/* PowerLimitMaximum */
+		15000,	/* PowerLimitMinimum */
+		15000,	/* PowerLimitMaximum */
 		1000,	/* TimeWindowMinimum */
 		1000,	/* TimeWindowMaximum */
 		1000	/* StepSize */
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index e255a7a..81f235f 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -215,7 +215,7 @@
 
 	register "speed_shift_enable" = "1"
 	register "dptf_enable" = "1"
-	register "tdp_pl2_override" = "7"
+	register "tdp_pl2_override" = "15"
 	register "tcc_offset" = "10"
 
 	device cpu_cluster 0 on

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I0838f4ec3026bc8bac814698043fa97cf6772cb4
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Duncan Laurie <dlaurie at chromium.org>