[coreboot-gerrit] Change in coreboot[master]: purism/librem13v2: Update USB config

[Youness Alaoui (Code Review)]

Hello Matt DeVillier,

I'd like you to do a code review.  Please visit

    https://review.coreboot.org/19940

to review the following change.


Change subject: purism/librem13v2: Update USB config
......................................................................

purism/librem13v2: Update USB config

Update devicetree USB config based on board spec.
Leave OC pins set to skip since info unavailable.

Change-Id: I2a4fe17ed7edacbbbaf56969f9d2801b45a20da9
Signed-off-by: Youness Alaoui <youness.alaoui at puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/mainboard/purism/librem13v2/devicetree.cb
1 file changed, 7 insertions(+), 9 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/19940/1

diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb
index ffd33a2..0defea0 100644
--- a/src/mainboard/purism/librem13v2/devicetree.cb
+++ b/src/mainboard/purism/librem13v2/devicetree.cb
@@ -155,17 +155,15 @@
 	# ClkReq for NVMe - Bruteforced (no other value works)
 	register "PcieRpClkReqNumber[8]" = "2"
 
-	register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)"	# Type-C Port 1
-	register "usb2_ports[1]" = "USB2_PORT_LONG(OC3)"	# Type-C Port 2
+	register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)"	# Type-C Port
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port (right)
 	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"		# Type-A Port
-	register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)"	# Camera
-	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"	# SD
+	register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)"	# Camera
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port (left)
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# SD
 
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"	# Type-C Port 1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)"	# Type-C Port 2
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"	# Type-A Port
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# SD
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-A Port (right)
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-C Port
 
 	register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"  # I2C4 is 1.8V
 

-- 
To view, visit https://review.coreboot.org/19940
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I2a4fe17ed7edacbbbaf56969f9d2801b45a20da9
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Youness Alaoui <snifikino at gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier at gmail.com>