[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Add missing PCH_DEV_PCIE* definitions

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19924 )

Change subject: soc/intel/skylake: Add missing PCH_DEV_PCIE* definitions
......................................................................

soc/intel/skylake: Add missing PCH_DEV_PCIE* definitions

This is required to add wake sources for PCIE PME events.

BUG=b:37088992

Change-Id: Ideecdf133908b0819d7d993e1c7df1a6578cb77d
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
---
M src/soc/intel/skylake/include/soc/pci_devs.h
1 file changed, 6 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/19924/1

diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h
index f51691c..9b86917 100644
--- a/src/soc/intel/skylake/include/soc/pci_devs.h
+++ b/src/soc/intel/skylake/include/soc/pci_devs.h
@@ -111,12 +111,18 @@
 #define  PCH_DEV_PCIE4		_PCH_DEV(PCIE, 3)
 #define  PCH_DEV_PCIE5		_PCH_DEV(PCIE, 4)
 #define  PCH_DEV_PCIE6		_PCH_DEV(PCIE, 5)
+#define  PCH_DEV_PCIE7		_PCH_DEV(PCIE, 6)
+#define  PCH_DEV_PCIE8		_PCH_DEV(PCIE, 7)
 
 #define PCH_DEV_SLOT_PCIE_1	0x1d
 #define  PCH_DEVFN_PCIE9	_PCH_DEVFN(PCIE_1, 0)
 #define  PCH_DEVFN_PCIE10	_PCH_DEVFN(PCIE_1, 1)
 #define  PCH_DEVFN_PCIE11	_PCH_DEVFN(PCIE_1, 2)
 #define  PCH_DEVFN_PCIE12	_PCH_DEVFN(PCIE_1, 3)
+#define  PCH_DEV_PCIE9		_PCH_DEV(PCIE_1, 0)
+#define  PCH_DEV_PCIE10	_PCH_DEV(PCIE_1, 1)
+#define  PCH_DEV_PCIE11	_PCH_DEV(PCIE_1, 2)
+#define  PCH_DEV_PCIE12	_PCH_DEV(PCIE_1, 3)
 
 #define PCH_DEV_SLOT_STORAGE	0x1e
 #define  PCH_DEVFN_UART0	_PCH_DEVFN(STORAGE, 0)

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Ideecdf133908b0819d7d993e1c7df1a6578cb77d
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Furquan Shaikh <furquan at google.com>