[coreboot-gerrit] Change in coreboot[master]: google/fizz: fixed the memory on ch1 is not detected

[Kane Chen (Code Review)]

Kane Chen has uploaded a new change for review. ( https://review.coreboot.org/19914 )

Change subject: google/fizz: fixed the memory on ch1 is not detected
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google/fizz: fixed the memory on ch1 is not detected

The spd address of sodimm on ch1 is 0xA4, but the current code will
only scan 0xA0 and 0xA2 if DIMM_MAX = 2
Also, MemorySpdPtr10 UPD for ch1 is not filled accordingly

Change-Id: Ia235b75870360d464839aa3b66045b421fd72ddf
Signed-off-by: Kane Chen <kane.chen at intel.com>
---
M src/mainboard/google/fizz/Kconfig
M src/mainboard/google/fizz/romstage.c
2 files changed, 2 insertions(+), 2 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/19914/1

diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig
index 2d2e6b7..e0d61f0 100644
--- a/src/mainboard/google/fizz/Kconfig
+++ b/src/mainboard/google/fizz/Kconfig
@@ -42,7 +42,7 @@
 
 config DIMM_MAX
 	int
-	default 2
+	default 4
 
 config DIMM_SPD_SIZE
 	int
diff --git a/src/mainboard/google/fizz/romstage.c b/src/mainboard/google/fizz/romstage.c
index be1d552..a1da494 100644
--- a/src/mainboard/google/fizz/romstage.c
+++ b/src/mainboard/google/fizz/romstage.c
@@ -36,7 +36,7 @@
 	get_spd_smbus(&blk);
 	mem_cfg->MemorySpdDataLen = blk.len;
 	mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
-	mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
+	mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2];
 
 	dump_spd_info(&blk);
 }

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia235b75870360d464839aa3b66045b421fd72ddf
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Kane Chen <kane.chen at intel.com>