[coreboot-gerrit] Change in coreboot[master]: pciexp_device: Remove useless write on a read-only register

[Youness Alaoui (Code Review)]

Youness Alaoui has uploaded a new change for review. ( https://review.coreboot.org/19901 )

Change subject: pciexp_device: Remove useless write on a read-only register
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pciexp_device: Remove useless write on a read-only register

The Role-Based Error Reporting is not a configurable field,
it's a read only field in the Device Capability register.
This code was old and comes from commit f6eb88ad but evidently
is not useful in any way. The PCIe Specification [1] states
that it's read-only and must always be set to 1.

I have also done tests on purism/librem13 hardware, trying to
change that value, without any success.

[1]: PCI Express Base Specification Revision 3.0
     Page 612

Change-Id: I729617a5c6f4f52dfc4c422df78379b309066399
Signed-off-by: Youness Alaoui <youness.alaoui at puri.sm>
---
M src/device/pciexp_device.c
1 file changed, 0 insertions(+), 5 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/19901/1

diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c
index fb2a284..bb9f9e3 100644
--- a/src/device/pciexp_device.c
+++ b/src/device/pciexp_device.c
@@ -362,11 +362,6 @@
 		lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL);
 		lnkctl |= apmc;
 		pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl);
-
-		/* Enable ASPM role based error reporting. */
-		devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP);
-		devcap |= PCI_EXP_DEVCAP_RBER;
-		pci_write_config32(endp, endp_cap + PCI_EXP_DEVCAP, devcap);
 	}
 
 	printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]);

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I729617a5c6f4f52dfc4c422df78379b309066399
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Youness Alaoui <snifikino at gmail.com>