[coreboot-gerrit] Change in coreboot[master]: purism/librem13v2: devicetree cleanup

[Youness Alaoui (Code Review)]

Hello Matt DeVillier,

I'd like you to do a code review.  Please visit

    https://review.coreboot.org/19896

to review the following change.


Change subject: purism/librem13v2: devicetree cleanup
......................................................................

purism/librem13v2: devicetree cleanup

disable DSP - not needed/used
set InternalGfx to default (1) since doesn't seem to matter
Disable PCI CLKREQ - fix hang on suspend due to wifi
remove TCC offset for -Y SoCs
set VrMbxCmd for U-series SoCs (Sentry, Kunimitsu)

Change-Id: If65fb0f23f71bea5d7c5f69b1cffe3a0a90c7f72
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/mainboard/purism/librem13v2/devicetree.cb
1 file changed, 4 insertions(+), 12 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/19896/1

diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb
index 5024cd1..f656fa8 100644
--- a/src/mainboard/purism/librem13v2/devicetree.cb
+++ b/src/mainboard/purism/librem13v2/devicetree.cb
@@ -34,7 +34,7 @@
 	register "SataPortsEnable[0]" = "1"
 	register "SataPortsEnable[2]" = "1"
 	register "EnableAzalia" = "1"
-	register "DspEnable" = "1"
+	register "DspEnable" = "0"
 	register "IoBufferOwnership" = "0"
 	register "EnableTraceHub" = "0"
 	register "XdciEnable" = "0"
@@ -46,7 +46,7 @@
 	register "ScsSdCardEnabled" = "0"
 	register "IshEnable" = "0"
 	register "PttSwitch" = "0"
-	register "InternalGfx" = "0"
+	register "InternalGfx" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
@@ -150,12 +150,6 @@
 	# Enable Root port 5 and 9
 	register "PcieRpEnable[4]" = "1"
 	register "PcieRpEnable[8]" = "1"
-	# Enable CLKREQ#
-	register "PcieRpClkReqSupport[4]" = "1"
-	#register "PcieRpClkReqSupport[8]" = "1"
-	# Default value from FSP programming guide
-	register "PcieRpClkReqNumber[4]" = "3"
-	#register "PcieRpClkReqNumber[8]" = "5"
 
 	register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)"	# Type-C Port
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port (right)
@@ -170,10 +164,8 @@
 	# PL2 override 25W
 	register "tdp_pl2_override" = "25"
 
-	register "tcc_offset" = "10"     # TCC of 90C
-
-	# Send an extra VR mailbox command for the supported MPS IMVP8 model
-	register "SendVrMbxCmd" = "1"
+	# Send an extra VR mailbox command for the PS4 exit issue
+	register "SendVrMbxCmd" = "2"
 
 	device cpu_cluster 0 on
 		device lapic 0 on end

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: If65fb0f23f71bea5d7c5f69b1cffe3a0a90c7f72
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Youness Alaoui <snifikino at gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier at gmail.com>