[coreboot-gerrit] Change in coreboot[master]: purism/librem13v2: Add support for NVMe devices

[Youness Alaoui (Code Review)]

Youness Alaoui has uploaded a new change for review. ( https://review.coreboot.org/19891 )

Change subject: purism/librem13v2: Add support for NVMe devices
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purism/librem13v2: Add support for NVMe devices

NVMe devices on the M.2 connector appear on the PCIe port #9

Change-Id: Icdc7f372c761001ae39143474b3c8c10a173ba67
Signed-off-by: Youness Alaoui <youness.alaoui at puri.sm>
---
M src/mainboard/purism/librem13v2/Kconfig
M src/mainboard/purism/librem13v2/devicetree.cb
2 files changed, 9 insertions(+), 5 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/19891/1

diff --git a/src/mainboard/purism/librem13v2/Kconfig b/src/mainboard/purism/librem13v2/Kconfig
index 7a69104..8f74e8d 100644
--- a/src/mainboard/purism/librem13v2/Kconfig
+++ b/src/mainboard/purism/librem13v2/Kconfig
@@ -2,6 +2,7 @@
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
+	select SYSTEM_TYPE_LAPTOP
 	select BOARD_ROMSIZE_KB_16384
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb
index ece7a4e..f37882a 100644
--- a/src/mainboard/purism/librem13v2/devicetree.cb
+++ b/src/mainboard/purism/librem13v2/devicetree.cb
@@ -29,10 +29,10 @@
 	register "ProbelessTrace" = "0"
 	register "EnableLan" = "0"
 	register "EnableSata" = "1"
-	register "SataSalpSupport" = "0"
+	register "SataSalpSupport" = "1"
 	register "SataMode" = "0"
 	register "SataPortsEnable[0]" = "1"
-	register "SataPortsEnable[1]" = "1"
+	register "SataPortsEnable[2]" = "1"
 	register "EnableAzalia" = "1"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "0"
@@ -147,12 +147,15 @@
 		.voltage_limit = 1520,
 	}"
 
-	# Enable Root port 5
+	# Enable Root port 5 and 9
 	register "PcieRpEnable[4]" = "1"
+	register "PcieRpEnable[8]" = "1"
 	# Enable CLKREQ#
-	register "PcieRpClkReqSupport[0]" = "1"
+	register "PcieRpClkReqSupport[4]" = "1"
+	register "PcieRpClkReqSupport[8]" = "1"
 	# Default value from FSP programming guide
 	register "PcieRpClkReqNumber[4]" = "3"
+	register "PcieRpClkReqNumber[8]" = "5"
 
 	register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)"	# Type-C Port
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port (right)
@@ -195,7 +198,7 @@
 		device pci 1c.5 off end # PCI Express Port 6
 		device pci 1c.6 off end # PCI Express Port 7
 		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 off end # PCI Express Port 9
+		device pci 1d.0 on  end # PCI Express Port 9
 		device pci 1d.1 off end # PCI Express Port 10
 		device pci 1d.2 off end # PCI Express Port 11
 		device pci 1d.3 off end # PCI Express Port 12

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Icdc7f372c761001ae39143474b3c8c10a173ba67
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Youness Alaoui <snifikino at gmail.com>