[coreboot-gerrit] Change in coreboot[master]: purism/librem13v2: update devicetree

[Youness Alaoui (Code Review)]

Hello Matt DeVillier,

I'd like you to do a code review.  Please visit

    https://review.coreboot.org/19886

to review the following change.


Change subject: purism/librem13v2: update devicetree
......................................................................

purism/librem13v2: update devicetree

Change-Id: Idd553c59da433c1ebfdae9f9057f0c2200a50f22
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/mainboard/purism/librem13v2/devicetree.cb
1 file changed, 5 insertions(+), 4 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/19886/1

diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb
index f306e7b..e51713b 100644
--- a/src/mainboard/purism/librem13v2/devicetree.cb
+++ b/src/mainboard/purism/librem13v2/devicetree.cb
@@ -28,10 +28,11 @@
 	# FSP Configuration
 	register "ProbelessTrace" = "0"
 	register "EnableLan" = "0"
-	register "EnableSata" = "0"
+	register "EnableSata" = "1"
 	register "SataSalpSupport" = "0"
 	register "SataMode" = "0"
-	register "SataPortsEnable[0]" = "0"
+	register "SataPortsEnable[0]" = "1"
+	register "SataPortsEnable[1]" = "1"
 	register "EnableAzalia" = "1"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
@@ -40,8 +41,8 @@
 	register "SsicPortEnable" = "0"
 	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "0"
-	register "ScsEmmcEnabled" = "1"
-	register "ScsEmmcHs400Enabled" = "1"
+	register "ScsEmmcEnabled" = "0"
+	register "ScsEmmcHs400Enabled" = "0"
 	register "ScsSdCardEnabled" = "0"
 	register "IshEnable" = "0"
 	register "PttSwitch" = "0"

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Idd553c59da433c1ebfdae9f9057f0c2200a50f22
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Youness Alaoui <snifikino at gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier at gmail.com>