[coreboot-gerrit] Change in coreboot[master]: purism/librem13v2: Add memory init code
Youness Alaoui (Code Review)
gerrit at coreboot.org
Wed May 24 23:32:14 CEST 2017
Youness Alaoui has uploaded a new change for review. ( https://review.coreboot.org/19884 )
Change subject: purism/librem13v2: Add memory init code
......................................................................
purism/librem13v2: Add memory init code
Adding code to setup the spd information from sodimm
Change-Id: I7869252710fafef8e207fd99ed0767e709045bd5
Signed-off-by: Youness Alaoui <youness.alaoui at puri.sm>
---
M src/mainboard/purism/librem13v2/Kconfig
M src/mainboard/purism/librem13v2/Makefile.inc
A src/mainboard/purism/librem13v2/bootblock_mainboard.c
M src/mainboard/purism/librem13v2/devicetree.cb
M src/mainboard/purism/librem13v2/gpio.h
M src/mainboard/purism/librem13v2/romstage.c
6 files changed, 102 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/19884/1
diff --git a/src/mainboard/purism/librem13v2/Kconfig b/src/mainboard/purism/librem13v2/Kconfig
index 2828398..ce772fb 100644
--- a/src/mainboard/purism/librem13v2/Kconfig
+++ b/src/mainboard/purism/librem13v2/Kconfig
@@ -44,4 +44,13 @@
string
default "8086,1916"
+config DIMM_MAX
+ int
+ default 1
+
+config DIMM_SPD_SIZE
+ int
+ default 512
+
+
endif
diff --git a/src/mainboard/purism/librem13v2/Makefile.inc b/src/mainboard/purism/librem13v2/Makefile.inc
index cbb4ee2..4e2997e 100644
--- a/src/mainboard/purism/librem13v2/Makefile.inc
+++ b/src/mainboard/purism/librem13v2/Makefile.inc
@@ -13,6 +13,7 @@
## GNU General Public License for more details.
##
+bootblock-y += bootblock_mainboard.c
romstage-y += pei_data.c
diff --git a/src/mainboard/purism/librem13v2/bootblock_mainboard.c b/src/mainboard/purism/librem13v2/bootblock_mainboard.c
new file mode 100644
index 0000000..627b4e8
--- /dev/null
+++ b/src/mainboard/purism/librem13v2/bootblock_mainboard.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <soc/gpio.h>
+#include "gpio.h"
+
+static void early_config_gpio(void)
+{
+ /* This is a hack for FSP because it does things in MemoryInit()
+ * which it shouldn't do. We have to prepare certain gpios here
+ * because of the brokenness in FSP. */
+ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
+
+void bootblock_mainboard_init(void)
+{
+ early_config_gpio();
+}
diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb
index c8569d9b..f306e7b 100644
--- a/src/mainboard/purism/librem13v2/devicetree.cb
+++ b/src/mainboard/purism/librem13v2/devicetree.cb
@@ -11,7 +11,7 @@
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed.
- register "gpe0_dw0" = "GPP_B"
+ register "gpe0_dw0" = "GPP_C"
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
@@ -165,7 +165,10 @@
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD
+ register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
+ register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
+ register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
diff --git a/src/mainboard/purism/librem13v2/gpio.h b/src/mainboard/purism/librem13v2/gpio.h
index bb3098b..01540b5 100644
--- a/src/mainboard/purism/librem13v2/gpio.h
+++ b/src/mainboard/purism/librem13v2/gpio.h
@@ -132,7 +132,8 @@
/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15),
/* GSPI0_CLK */ PAD_CFG_NC_RXINV(GPP_B16, LEVEL),
/* GSPI0_MISO */ PAD_CFG_NC_RXINV(GPP_B17, EDGE),
-/* GSPI0_MOSI */ PAD_CFG_GPI_ACPI_SCI_LEVEL(GPP_B18, 20K_PU, PLTRST, YES),
+/* GSPI0_MOSI */ PAD_CFG_GPI_ACPI_SCI_LEVEL(GPP_B18, 20K_PU,
+ PLTRST, YES),
/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19),
/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20),
/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21),
@@ -223,9 +224,7 @@
/* I2C3_SDA */ PAD_CFG_NC_1V8(GPP_F6),
/* I2C3_SCL */ PAD_CFG_NC_1V8(GPP_F7),
/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
-/* AUDIO1V8_SDA */
/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
-/* AUDIO1V8_SCL */
/* I2C5_SDA */ PAD_CFG_NC_1V8(GPP_F10),
/* I2C5_SCL */ PAD_CFG_NC_1V8(GPP_F11),
/* EMMC_CMD */ PAD_CFG_NC(GPP_F12),
@@ -264,6 +263,25 @@
/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
};
+/* Early pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+/* SRCCLKREQ0# */ PAD_CFG_NF_EVCFG(GPP_B5, NONE, DEEP, NF1, LEVEL),
+/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
+/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
+/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
+/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
+/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
+/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
+/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+/* SMBDATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1),
+/* SMBALERT# */ PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP),
+};
+
#endif
#endif
diff --git a/src/mainboard/purism/librem13v2/romstage.c b/src/mainboard/purism/librem13v2/romstage.c
index da1c4c3..3505467 100644
--- a/src/mainboard/purism/librem13v2/romstage.c
+++ b/src/mainboard/purism/librem13v2/romstage.c
@@ -16,10 +16,12 @@
*/
#include <string.h>
+#include <assert.h>
#include <arch/acpi.h>
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
#include <soc/romstage.h>
+#include <spd_bin.h>
void mainboard_romstage_entry(struct romstage_params *params)
{
@@ -28,3 +30,37 @@
/* Initliaze memory */
romstage_common(params);
}
+
+void mainboard_memory_init_params(struct romstage_params *params,
+ MEMORY_INIT_UPD *memory_params)
+{
+ struct spd_block blk;
+
+ memory_params->DqPinsInterleaved = 1;
+ printk(BIOS_INFO, "In mainboard_memory_init_params\n");
+ get_spd_smbus(&blk);
+ dump_spd_info(&blk);
+ memory_params->MemorySpdDataLen = blk.len;
+ if (blk.spd_array[0][0] != 0)
+ memory_params->MemorySpdPtr00 = (u32)blk.spd_array[0];
+ if (blk.spd_array[1][0] != 0)
+ memory_params->MemorySpdPtr10 = (u32)blk.spd_array[1];
+ if (blk.spd_array[2][0] != 0)
+ memory_params->MemorySpdPtr01 = (u32)blk.spd_array[2];
+ if (blk.spd_array[3][0] != 0)
+ memory_params->MemorySpdPtr11 = (u32)blk.spd_array[3];
+
+ memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0],
+ sizeof(params->pei_data->dq_map[0]));
+ memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1],
+ sizeof(params->pei_data->dq_map[1]));
+ memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0],
+ sizeof(params->pei_data->dqs_map[0]));
+ memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1],
+ sizeof(params->pei_data->dqs_map[1]));
+ memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor,
+ sizeof(params->pei_data->RcompResistor));
+ memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget,
+ sizeof(params->pei_data->RcompTarget));
+
+}
--
To view, visit https://review.coreboot.org/19884
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: newchange
Gerrit-Change-Id: I7869252710fafef8e207fd99ed0767e709045bd5
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Youness Alaoui <snifikino at gmail.com>
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