[coreboot-gerrit] Change in coreboot[master]: nb/intel/x4x: Rename a things that are not ddr2 specific
Arthur Heymans (Code Review)
gerrit at coreboot.org
Wed May 24 22:10:34 CEST 2017
Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19870 )
Change subject: nb/intel/x4x: Rename a things that are not ddr2 specific
......................................................................
nb/intel/x4x: Rename a things that are not ddr2 specific
Change-Id: Ib3d10014f530905155e56fc52706edb4ab9f5630
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/northbridge/intel/x4x/Makefile.inc
M src/northbridge/intel/x4x/raminit.c
R src/northbridge/intel/x4x/raminit_ddr23.c
M src/northbridge/intel/x4x/x4x.h
4 files changed, 19 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/19870/1
diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc
index 86ecf7b..ae8d388 100644
--- a/src/northbridge/intel/x4x/Makefile.inc
+++ b/src/northbridge/intel/x4x/Makefile.inc
@@ -18,7 +18,7 @@
romstage-y += early_init.c
romstage-y += raminit.c
-romstage-y += raminit_ddr2.c
+romstage-y += raminit_ddr23.c
romstage-y += ram_calc.c
romstage-y += spd_ddr2_decode.c
romstage-y += spd_ddr3_decode.c
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index b2bc280..f3b4928 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -263,17 +263,7 @@
print_selected_timings(&s);
find_dimm_config(&s);
- switch (s.spd_type) {
- case DDR2:
- raminit_ddr2(&s);
- break;
- case DDR3:
- // FIXME Add: raminit_ddr3(&s);
- break;
- default:
- die("Unknown DDR type\n");
- break;
- }
+ do_raminit(&s);
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 & ~0x80);
diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr23.c
similarity index 98%
rename from src/northbridge/intel/x4x/raminit_ddr2.c
rename to src/northbridge/intel/x4x/raminit_ddr23.c
index e663564..9cb29ef 100644
--- a/src/northbridge/intel/x4x/raminit_ddr2.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -68,7 +68,7 @@
return (u8)(pos & 0xff);
}
-static void clkcross_ddr2(struct sysinfo *s)
+static void program_crossclock(struct sysinfo *s)
{
u8 i, j;
MCHBAR16(0xc1c) = MCHBAR16(0xc1c) | (1 << 15);
@@ -152,7 +152,7 @@
MCHBAR32(0x70c) = clkxtab[i][j][12];
}
-static void setioclk_ddr2(struct sysinfo *s)
+static void setioclk_dram(struct sysinfo *s)
{
MCHBAR32(0x1bc) = 0x08060402;
MCHBAR16(0x1c0) = MCHBAR16(0x1c0) | 0x200;
@@ -180,7 +180,7 @@
MCHBAR32(0x994) = MCHBAR32(0x994) | (1 << 31);
}
-static void launch_ddr2(struct sysinfo *s)
+static void launch_dram(struct sysinfo *s)
{
u8 i;
u32 launch1 = 0x58001117;
@@ -379,7 +379,7 @@
setting->tap;
}
-static void timings_ddr2(struct sysinfo *s)
+static void program_timings(struct sysinfo *s)
{
u8 i;
u8 twl, ta1, ta2, ta3, ta4;
@@ -604,7 +604,7 @@
MCHBAR8(0x6c4) = (MCHBAR8(0x6c4) & ~0x7) | 0x2;
}
-static void dll_ddr2(struct sysinfo *s)
+static void program_dll(struct sysinfo *s)
{
u8 i, j, r, reg8, clk, async;
u16 reg16 = 0;
@@ -973,7 +973,7 @@
MCHBAR8(0x130) = MCHBAR8(0x130) | 1;
}
-static void odt_ddr2(struct sysinfo *s)
+static void program_odt(struct sysinfo *s)
{
u8 i;
u16 odt[16][2] = {
@@ -1003,7 +1003,7 @@
}
}
-static void dojedec_ddr2(u8 r, u8 ch, u8 cmd, u16 val)
+static void send_jedec_cmd(u8 r, u8 ch, u8 cmd, u16 val)
{
u32 addr = (ch << 29) | (r*0x08000000);
volatile u32 rubbish;
@@ -1075,7 +1075,7 @@
default:
break;
}
- dojedec_ddr2(r + ch*4, ch, jedec[i][0], v);
+ send_jedec_cmd(r + ch*4, ch, jedec[i][0], v);
udelay(1);
//printk(BIOS_DEBUG, "Jedec step %d\n", i);
}
@@ -1783,7 +1783,7 @@
MCHBAR8(0x561 + (lane << 2)) = MCHBAR8(0x561 + (lane << 2)) & ~(1 << 3);
}
-void raminit_ddr2(struct sysinfo *s)
+void do_raminit(struct sysinfo *s)
{
u8 ch;
u8 r, bank;
@@ -1813,25 +1813,24 @@
mdelay(250);
// Program clock crossing
- clkcross_ddr2(s);
+ program_crossclock(s);
printk(BIOS_DEBUG, "Done clk crossing\n");
- // DDR2 IO
if (s->boot_path != BOOT_PATH_WARM_RESET) {
- setioclk_ddr2(s);
+ setioclk_dram(s);
printk(BIOS_DEBUG, "Done I/O clk\n");
}
// Grant to launch
- launch_ddr2(s);
+ launch_dram(s);
printk(BIOS_DEBUG, "Done launch\n");
- // Program DDR2 timings
- timings_ddr2(s);
+ // Program DRAM timings
+ program_timings(s);
printk(BIOS_DEBUG, "Done timings\n");
// Program DLL
- dll_ddr2(s);
+ program_dll(s);
// RCOMP
if (s->boot_path != BOOT_PATH_WARM_RESET) {
@@ -1840,7 +1839,7 @@
}
// ODT
- odt_ddr2(s);
+ program_odt(s);
printk(BIOS_DEBUG, "Done ODT\n");
// RCOMP update
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index 43e37ef..621a685 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -343,7 +343,7 @@
u32 decode_igd_gtt_size(u32 gsm);
u8 decode_pciebar(u32 *const base, u32 *const len);
void sdram_initialize(int boot_path, const u8 *spd_map);
-void raminit_ddr2(struct sysinfo *);
+void do_raminit(struct sysinfo *);
u32 fsb2mhz(u32 speed);
u32 ddr2mhz(u32 speed);
void select_cas_dramfreq_ddr2(struct sysinfo *s,
--
To view, visit https://review.coreboot.org/19870
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib3d10014f530905155e56fc52706edb4ab9f5630
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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