[coreboot-gerrit] Change in coreboot[master]: google/kahlee: Update PCIe link/lane configuration
Marc Jones (Code Review)
gerrit at coreboot.org
Wed May 24 01:07:15 CEST 2017
Marc Jones has uploaded a new change for review. ( https://review.coreboot.org/19838 )
Change subject: google/kahlee: Update PCIe link/lane configuration
......................................................................
google/kahlee: Update PCIe link/lane configuration
Enable:
GPP0 x1 - WLan
GPP1 x1 - Card Reader
Change-Id: Idbfc2a3260b85949810bdd8dc904e59f8a779e48
Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
M src/mainboard/google/kahlee/OemCustomize.c
1 file changed, 18 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/19838/1
diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c
index 99d0594..4fcc17e 100644
--- a/src/mainboard/google/kahlee/OemCustomize.c
+++ b/src/mainboard/google/kahlee/OemCustomize.c
@@ -18,56 +18,56 @@
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
static const PCIe_PORT_DESCRIPTOR PortList [] = {
- /* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for x4 slot */
+ /* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for NC*/
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 4, 7),
- PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 1,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmL0sL1, 0x04, 0)
},
- /* Initialize Port descriptor (PCIe port, Lanes 1:0, D2F2) for M.2 */
+ /* Initialize Port descriptor (PCIe port, Lanes 0:0, D2F2) for WLAN */
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 0, 1),
- PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 2,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
- AspmL0sL1, 0x17, 0)
+ AspmL0sL1, 0x2, 0)
},
+ /* Initialize Port descriptor (PCIe port, Lanes 1:1, D2F3) for Card Reader */
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 1, 1),
- PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 3,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
- AspmL0sL1, 0x17, 0)
+ AspmL0sL1, 0x3, 0)
},
- /* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for x1 slot */
+ /* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for NC */
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),
- PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 2, 2),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 4,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
- AspmL0sL1, 0x13, 0)
+ AspmL0sL1, 0, 0)
},
- /* Initialize Port descriptor (PCIe port, Lane3, D2F5) for SD */
+ /* Initialize Port descriptor (PCIe port, Lane3, D2F5) for NC */
{
DESCRIPTOR_TERMINATE_LIST,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
- PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 3, 3),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 5,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
- AspmL0sL1, 0x16, 0)
+ AspmL0sL1, 0, 0)
},
- /* Initialize Port descriptor (PCIe port, Lane 1, D2F3) for M.2 */
};
static const PCIe_DDI_DESCRIPTOR DdiList [] = {
--
To view, visit https://review.coreboot.org/19838
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Idbfc2a3260b85949810bdd8dc904e59f8a779e48
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Marc Jones <marc at marcjonesconsulting.com>
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