[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: [WIP]Add Intel common CPU code

Subrata Banik (Code Review) gerrit at coreboot.org
Tue May 23 20:55:39 CEST 2017


Subrata Banik has posted comments on this change. ( https://review.coreboot.org/19540 )

Change subject: soc/intel/common/block: [WIP]Add Intel common CPU code
......................................................................


Patch Set 8:

(20 comments)

https://review.coreboot.org/#/c/19540/8/src/soc/intel/common/block/cpu/Kconfig
File src/soc/intel/common/block/cpu/Kconfig:

PS8, Line 4: Intel Common CPU Model Support.
can you please add little bit more like below.


https://review.coreboot.org/#/c/19540/8/src/soc/intel/common/block/cpu/cpu.c
File src/soc/intel/common/block/cpu/cpu.c:

PS8, Line 18: #include <assert.h>
            : #include <bootstate.h>
            : #include <console/console.h>
            : #include <cpu/cpu.h>
            : #include <cpu/x86/mtrr.h>
            : #include <cpu/x86/msr.h>
            : #include <cpu/x86/lapic.h>
            : #include <cpu/x86/mp.h>
            : #include <cpu/intel/microcode.h>
            : #include <cpu/intel/speedstep.h>
            : #include <cpu/intel/turbo.h>
            : #include <cpu/x86/cache.h>
            : #include <cpu/x86/name.h>
            : #include <cpu/x86/smm.h>
            : #include <delay.h>
            : #include <device/device.h>
            : #include <device/pci.h>
            : #include <intelblocks/cpu.h>
            : #include <intelblocks/msr.h>
            : #include <intelblocks/smm.h>
            : #include <pc80/mc146818rtc.h>
            : #include <soc/cpu.h>
            : #include <soc/pci_devs.h>
            : #include <soc/systemagent.h>
            : #include <string.h>
let see if we can optimize this


PS8, Line 48: 
            : 	eax = cpuid_eax(CPUID_LEAF_PM);
            : 
            : 	msr = rdmsr(MSR_IA32_MISC_ENABLES);
            : 	eax &= 0x2;
            : 	if ((!eax) && ((msr.hi & BURST_MODE_DISABLE) == 0)) {
            : 		/* Burst Mode has been factory configured as disabled
            : 		 * and is not available in this physical processor
            : 		 * package.
            : 		 */
            : 		printk(BIOS_DEBUG, "Burst Mode is factory disabled\n");
            : 		return;
            : 	}
            : 
            : 	/* Enable burst mode */
            : 	msr.hi &= ~BURST_MODE_DISABLE;
            : 	wrmsr(MSR_IA32_MISC_ENABLES, msr);
can this be put into a function and call as enable/disable turbo for romstage as i understood you don't want to use turbo.c file which gets included in ramstage


PS8, Line 66: 	/* Enable speed step. */
            : 	msr = rdmsr(MSR_IA32_MISC_ENABLES);
            : 	msr.lo |= 1 << 16;
            : 	wrmsr(MSR_IA32_MISC_ENABLES, msr);
make as function so, mp init feature programming can use this.


https://review.coreboot.org/#/c/19540/8/src/soc/intel/common/block/cpu/cpu_early.c
File src/soc/intel/common/block/cpu/cpu_early.c:

Line 53: }
can we also have a int get_nominal_ratio() {
flex_ratio = rdmsr(MSR_FLEX_RATIO);
nominal_ratio = ((flex_ratio.lo >> 8) & 0xff) 

return nominal_ratio;
}


PS8, Line 94: #if !ENV_RAMSTAGE
why guard?


PS8, Line 150: void set_P_State_to_turbo_ratio(void)
no camel case


PS8, Line 170: set_P_State_to_nominal_TDP_ratio
same


PS8, Line 189: set_P_State_to_max_non_turbo_ratio
-same


https://review.coreboot.org/#/c/19540/8/src/soc/intel/common/block/cpu/smmrelocate.c
File src/soc/intel/common/block/cpu/smmrelocate.c:

PS8, Line 34: #include "chip.h"
do we need?


https://review.coreboot.org/#/c/19540/8/src/soc/intel/common/block/include/intelblocks/cpu.h
File src/soc/intel/common/block/include/intelblocks/cpu.h:

PS8, Line 19: #include <rules.h>
remove this


PS8, Line 25: 		
one tab less?


PS8, Line 39: #if !ENV_RAMSTAGE
don't need?


https://review.coreboot.org/#/c/19540/8/src/soc/intel/common/block/include/intelblocks/msr.h
File src/soc/intel/common/block/include/intelblocks/msr.h:

PS8, Line 47: 		
one tab less


PS8, Line 53: 	0x40
(1 << 6)


PS8, Line 124:  
use tab?


PS8, Line 124: #define SMRR_SUPPORTED (1<<11)
             : #define PRMRR_SUPPORTED (1<<12)
lets analyze if you can move this into mtrr.h


https://review.coreboot.org/#/c/19540/8/src/soc/intel/common/block/include/intelblocks/smm.h
File src/soc/intel/common/block/include/intelblocks/smm.h:

PS8, Line 5: 2015
2017


PS8, Line 17: _
remove this


PS8, Line 22: #include <fsp/memmap.h>
            : #include <soc/gpio.h>
why we need this


-- 
To view, visit https://review.coreboot.org/19540
To unsubscribe, visit https://review.coreboot.org/settings

Gerrit-MessageType: comment
Gerrit-Change-Id: I2f80c42132d9ea738be4051d2395e9e51ac153f8
Gerrit-PatchSet: 8
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik at intel.com>
Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein at intel.com>
Gerrit-Reviewer: Cole Nelson <colex.nelson at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati at intel.com>
Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi at intel.com>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Shaunak Saha <shaunak.saha at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: V Sowmya <v.sowmya at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma at intel.com>
Gerrit-HasComments: Yes



More information about the coreboot-gerrit mailing list