[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Use common systemagent code
Subrata Banik (Code Review)
gerrit at coreboot.org
Fri May 19 16:46:53 CEST 2017
Subrata Banik has uploaded a new change for review. ( https://review.coreboot.org/19795 )
Change subject: soc/intel/apollolake: Use common systemagent code
......................................................................
soc/intel/apollolake: Use common systemagent code
This patch perform resource mapping for PCI,
fixed MMIO, DRAM and IMR's based on inputs given by SoC.
TEST=Ensure PCI root bridge 0:0:0 memory resource allocation
remains same between previous implementation and current
implementation.
Change-Id: I15a3b2fc46ec9063b54379d41996b9a1d612cfd2
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/chip.c
M src/soc/intel/apollolake/include/soc/systemagent.h
M src/soc/intel/apollolake/northbridge.c
M src/soc/intel/apollolake/romstage.c
5 files changed, 76 insertions(+), 167 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/19795/1
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 56f0d20..7c95e1c 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -50,6 +50,7 @@
select RELOCATABLE_RAMSTAGE # Build fails if this is not selected
select RTC
select SMM_TSEG
+ select SA_ENABLE_IMR
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index da60827..90a1ba9 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -219,7 +219,6 @@
uint32_t power_unit;
uint32_t tdp, min_power, max_power;
uint32_t pl2_val;
- uint32_t *rapl_mmio_reg;
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
@@ -272,15 +271,12 @@
printk(BIOS_INFO, "RAPL PL2 %d.%dW\n", pl2_val / power_unit,
100 * (pl2_val % power_unit) / power_unit);
- /* Get the MMIO address */
- rapl_mmio_reg = (void *)(uintptr_t) (MCH_BASE_ADDRESS +
- MCHBAR_RAPL_PPL);
/* Setting RAPL MMIO register for Power limits.
* RAPL driver is using MSR instead of MMIO.
* So, disabled LIMIT_EN bit for MMIO. */
- write32(rapl_mmio_reg, limit.lo & ~(PKG_POWER_LIMIT_EN));
- write32(rapl_mmio_reg + 1, limit.hi & ~(PKG_POWER_LIMIT_EN));
+ MCHBAR32(MCHBAR_RAPL_PPL) = limit.lo & ~(PKG_POWER_LIMIT_EN);
+ MCHBAR32(MCHBAR_RAPL_PPL + 4) = limit.hi & ~(PKG_POWER_LIMIT_EN);
}
static void soc_init(void *data)
diff --git a/src/soc/intel/apollolake/include/soc/systemagent.h b/src/soc/intel/apollolake/include/soc/systemagent.h
index 1ed0a1f..d6c7390 100644
--- a/src/soc/intel/apollolake/include/soc/systemagent.h
+++ b/src/soc/intel/apollolake/include/soc/systemagent.h
@@ -20,12 +20,6 @@
#include <intelblocks/systemagent.h>
-/* IMR registers are found under MCHBAR. */
-#define MCHBAR_IMR0BASE 0x6870
-#define MCHBAR_IMR0MASK 0x6874
-#define MCH_IMR_PITCH 0x20
-#define MCH_NUM_IMRS 20
-
/* RAPL Package Power Limit register under MCHBAR. */
#define PUNIT_THERMAL_DEVICE_IRQ 0x700C
#define PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER 0x18
@@ -44,5 +38,28 @@
/* Must be last. */
MAX_MAP_ENTRIES
};
+
+/* IMR registers are found under MCHBAR. */
+#define IMR0_BASE 0x6870
+#define IMR1_BASE 0x6890
+#define IMR2_BASE 0x68B0
+#define IMR3_BASE 0x68D0
+#define IMR4_BASE 0x68F0
+#define IMR5_BASE 0x6910
+#define IMR6_BASE 0x6930
+#define IMR7_BASE 0x6950
+#define IMR8_BASE 0x6970
+#define IMR9_BASE 0x6990
+#define IMR10_BASE 0x69B0
+#define IMR11_BASE 0x69D0
+#define IMR12_BASE 0x69F0
+#define IMR13_BASE 0x6A10
+#define IMR14_BASE 0x6A30
+#define IMR15_BASE 0x6A50
+#define IMR16_BASE 0x6A70
+#define IMR17_BASE 0x6A90
+#define IMR18_BASE 0x6AB0
+#define IMR19_BASE 0x6AD0
+
#define SOC_SA_IMR_RESOURCES 20
#endif /* SOC_APOLLOLAKE_SYSTEMAGENT_H */
diff --git a/src/soc/intel/apollolake/northbridge.c b/src/soc/intel/apollolake/northbridge.c
index 9519603..70893e6 100644
--- a/src/soc/intel/apollolake/northbridge.c
+++ b/src/soc/intel/apollolake/northbridge.c
@@ -20,150 +20,42 @@
#include <soc/iomap.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <intelblocks/systemagent.h>
#include <soc/systemagent.h>
#include <soc/pci_ids.h>
-static uint32_t get_bar(device_t dev, unsigned int index)
-{
- uint32_t bar;
-
- bar = pci_read_config32(dev, index);
-
- /* If not enabled return 0 else strip enabled bit */
- return (bar & 1) ? (bar & ~1) : 0;
-}
-
-static int mc_add_fixed_mmio_resources(device_t dev, int index)
-{
- unsigned long addr;
-
- /* PCI extended config region */
- addr = ALIGN_DOWN(get_bar(dev, PCIEXBAR), 256*MiB) / KiB;
- mmio_resource(dev, index++, addr, CONFIG_SA_PCIEX_LENGTH / KiB);
-
- /* Memory Controller Hub */
- addr = ALIGN_DOWN(get_bar(dev, MCHBAR), 32*KiB) / KiB;
- mmio_resource(dev, index++, addr, MCH_BASE_SIZE / KiB);
-
- return index;
-}
-
-static bool is_imr_enabled(uint32_t imr_base_reg)
-{
- return !!(imr_base_reg & (1 << 31));
-}
-
-static void imr_resource(device_t dev, int idx, uint32_t base, uint32_t mask)
-{
- uint32_t base_k, size_k;
- /* Bits 28:0 encode the base address bits 38:10, hence the KiB unit. */
- base_k = (base & 0x0fffffff);
- /* Bits 28:0 encode the AND mask used for comparison, in KiB. */
- size_k = ((~mask & 0x0fffffff) + 1);
- /*
- * IMRs sit in lower DRAM. Mark them cacheable, otherwise we run
- * out of MTRRs. Memory reserved by IMRs is not usable for host
- * so mark it reserved.
- */
- reserved_ram_resource(dev, idx, base_k, size_k);
-}
-
-static int mc_add_imr_resources(device_t dev, int index)
-{
- uint8_t *mchbar;
- size_t i, imr_offset;
- uint32_t base, mask;
-
- mchbar = (void *)(ALIGN_DOWN(get_bar(dev, MCHBAR), 32*KiB));
-
- for (i = 0; i < MCH_NUM_IMRS; i++) {
- imr_offset = i * MCH_IMR_PITCH;
- base = read32(mchbar + imr_offset + MCHBAR_IMR0BASE);
- mask = read32(mchbar + imr_offset + MCHBAR_IMR0MASK);
-
- if (is_imr_enabled(base))
- imr_resource(dev, index++, base, mask);
- }
-
- return index;
-}
-
-
-static int mc_add_dram_resources(device_t dev, int index)
-{
- unsigned long base_k, size_k;
- uint32_t bgsm, bdsm, tolud, tseg;
- uint64_t touud;
-
- bgsm = ALIGN_DOWN(pci_read_config32(dev, BGSM), MiB);
- bdsm = ALIGN_DOWN(pci_read_config32(dev, BDSM), MiB);
- tolud = ALIGN_DOWN(pci_read_config32(dev, TOLUD), MiB);
- tseg = ALIGN_DOWN(pci_read_config32(dev, TSEG), MiB);
-
- /* TOUUD is naturally a 64 bit integer */
- touud = pci_read_config32(dev, TOUUD + sizeof(uint32_t));
- touud <<= 32;
- touud |= ALIGN_DOWN(pci_read_config32(dev, TOUUD), MiB);
-
- /* 0 -> 0xa0000: 640kb of DOS memory. Not enough for anybody nowadays */
- ram_resource(dev, index++, 0, 640);
-
- /* 0xa0000 - 0xbffff: legacy VGA */
- mmio_resource(dev, index++, 640, 128);
-
- /* 0xc0000 -> 0xfffff: leave without e820 entry, as it has special uses
- * 0x100000 -> top_of_ram
- */
- base_k = 1024;
- size_k = (tseg / KiB) - base_k;
- ram_resource(dev, index++, base_k, size_k);
-
- /* TSEG -> BGSM */
- reserved_ram_resource(dev, index++, tseg / KiB, (bgsm - tseg) / KiB);
-
- /* BGSM -> BDSM */
- mmio_resource(dev, index++, bgsm / KiB, (bdsm - bgsm) / KiB);
-
- /* BDSM -> TOLUD */
- mmio_resource(dev, index++, bdsm / KiB, (tolud - bdsm) / KiB);
-
- /* 4G -> TOUUD */
- base_k = 4ULL*GiB / KiB;
- size_k = (touud / KiB) - base_k;
- ram_resource(dev, index++, base_k, size_k);
-
-
- return index;
-}
-
-static void northbridge_read_resources(device_t dev)
-{
-
- int index = 0;
- /* Read standard PCI resources. */
- pci_dev_read_resources(dev);
-
- /* Add all fixed MMIO resources. */
- index = mc_add_fixed_mmio_resources(dev, index);
-
- /* Calculate and add DRAM resources. */
- index = mc_add_dram_resources(dev, index);
-
- /* Add the isolated memory ranges (IMRs). */
- mc_add_imr_resources(dev, index);
-
-}
-
-static struct device_operations northbridge_ops = {
- .read_resources = northbridge_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = DEVICE_NOOP,
- .enable = DEVICE_NOOP
+struct sa_mmio_descriptor sa_fixed_resources[SOC_SA_FIXED_RESOURCES] = {
+ { PCIEXBAR, 0, get_pcie_base_addr, "PCIEXBAR" },
+ { MCHBAR, MCH_BASE_SIZE, get_base_addr, "MCHBAR" },
};
-static const struct pci_driver northbridge_driver __pci_driver = {
- .ops = &northbridge_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_APOLLOLAKE_NB
+struct sa_map_entry sa_memory_map[MAX_MAP_ENTRIES] = {
+ [SA_TOUUD_REG] = SA_MAP_ENTRY_BASE_64(TOUUD, "TOUUD"),
+ [SA_TOLUD_REG] = SA_MAP_ENTRY_BASE_32(TOLUD, "TOLUD"),
+ [SA_BDSM_REG] = SA_MAP_ENTRY_BASE_32(BDSM, "BDSM"),
+ [SA_BGSM_REG] = SA_MAP_ENTRY_BASE_32(BGSM, "BGSM"),
+ [SA_TSEG_REG] = SA_MAP_ENTRY_BASE_32(TSEG, "TESGMB"),
+};
+
+struct sa_mmio_descriptor sa_imr_resources[SOC_SA_IMR_RESOURCES] = {
+ { IMR0_BASE, 0, get_base_addr_from_mchbar, "IMR0 BASE" },
+ { IMR1_BASE, 0, get_base_addr_from_mchbar, "IMR1 BASE" },
+ { IMR2_BASE, 0, get_base_addr_from_mchbar, "IMR2 BASE" },
+ { IMR3_BASE, 0, get_base_addr_from_mchbar, "IMR3 BASE" },
+ { IMR4_BASE, 0, get_base_addr_from_mchbar, "IMR4 BASE" },
+ { IMR5_BASE, 0, get_base_addr_from_mchbar, "IMR5 BASE" },
+ { IMR6_BASE, 0, get_base_addr_from_mchbar, "IMR6 BASE" },
+ { IMR7_BASE, 0, get_base_addr_from_mchbar, "IMR7 BASE" },
+ { IMR8_BASE, 0, get_base_addr_from_mchbar, "IMR8 BASE" },
+ { IMR9_BASE, 0, get_base_addr_from_mchbar, "IMR9 BASE" },
+ { IMR10_BASE, 0, get_base_addr_from_mchbar, "IMR10 BASE" },
+ { IMR11_BASE, 0, get_base_addr_from_mchbar, "IMR11 BASE" },
+ { IMR12_BASE, 0, get_base_addr_from_mchbar, "IMR12 BASE" },
+ { IMR13_BASE, 0, get_base_addr_from_mchbar, "IMR13 BASE" },
+ { IMR14_BASE, 0, get_base_addr_from_mchbar, "IMR14 BASE" },
+ { IMR15_BASE, 0, get_base_addr_from_mchbar, "IMR15 BASE" },
+ { IMR16_BASE, 0, get_base_addr_from_mchbar, "IMR16 BASE" },
+ { IMR17_BASE, 0, get_base_addr_from_mchbar, "IMR17 BASE" },
+ { IMR18_BASE, 0, get_base_addr_from_mchbar, "IMR18 BASE" },
+ { IMR19_BASE, 0, get_base_addr_from_mchbar, "IMR19 BASE" },
};
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index aebed9a..82a9ad6 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -31,6 +31,7 @@
#include <fsp/api.h>
#include <fsp/memmap.h>
#include <fsp/util.h>
+#include <intelblocks/systemagent.h>
#include <reset.h>
#include <soc/cpu.h>
#include <soc/intel/common/mrc_cache.h>
@@ -80,8 +81,13 @@
*/
static void soc_early_romstage_init(void)
{
- /* Set MCH base address and enable bit */
- pci_write_config32(SA_DEV_ROOT, MCHBAR, MCH_BASE_ADDRESS | 1);
+ struct sa_set_mmio_descriptor soc_fixed_set_resources[] = {
+ { MCHBAR, MCH_BASE_ADDRESS, set_base_addr, \
+ "MCHBAR"},
+ };
+
+ romstage_systemagent_early_init(soc_fixed_set_resources,
+ ARRAY_SIZE(soc_fixed_set_resources));
/* Enable decoding for HPET. Needed for FSP global pointer storage */
pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
@@ -140,13 +146,10 @@
* Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR).
* Enable all cores here.
*/
- write32((void *)(MCH_BASE_ADDRESS + CORE_DISABLE_MASK),
- 0x0);
+ MCHBAR32(CORE_DISABLE_MASK) = 0x0;
- void *bios_rest_cpl = (void *)(MCH_BASE_ADDRESS +
- BIOS_RESET_CPL);
/* P-Unit bring up */
- reg = read32(bios_rest_cpl);
+ reg = MCHBAR32(BIOS_RESET_CPL);
if (reg == 0xffffffff) {
/* P-unit not found */
printk(BIOS_DEBUG, "Punit MMIO not available\n");
@@ -156,24 +159,24 @@
pci_write_config8(SA_DEV_PUNIT, PCI_INTERRUPT_PIN, 0x2);
/* Set PUINT IRQ to 24 and INTPIN LOCK */
- write32((void *)(MCH_BASE_ADDRESS + PUNIT_THERMAL_DEVICE_IRQ),
- PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER |
- PUINT_THERMAL_DEVICE_IRQ_LOCK);
+ MCHBAR32(PUNIT_THERMAL_DEVICE_IRQ) =
+ PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER |
+ PUINT_THERMAL_DEVICE_IRQ_LOCK;
- data = read32((void *)(MCH_BASE_ADDRESS + 0x7818));
+ data = MCHBAR32(0x7818);
data &= 0xFFFFE01F;
data |= 0x20 | 0x200;
- write32((void *)(MCH_BASE_ADDRESS + 0x7818), data);
+ MCHBAR32(0x7818) = data;
/* Stage0 BIOS Reset Complete (RST_CPL) */
- write32(bios_rest_cpl, 0x1);
+ enable_bios_reset_cpl();
/*
* Poll for bit 8 in same reg (RST_CPL).
* We wait here till 1 ms for the bit to get set.
*/
stopwatch_init_msecs_expire(&sw, 1);
- while (!(read32(bios_rest_cpl) & 0x100)) {
+ while (!(MCHBAR32(BIOS_RESET_CPL) & 0x100)) {
if (stopwatch_expired(&sw)) {
printk(BIOS_DEBUG,
"Failed to set RST_CPL bit\n");
--
To view, visit https://review.coreboot.org/19795
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I15a3b2fc46ec9063b54379d41996b9a1d612cfd2
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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