[coreboot-gerrit] Change in coreboot[master]: Consolidate reset API, add generic reset_prepare mechanism
Julius Werner (Code Review)
gerrit at coreboot.org
Fri May 19 02:46:19 CEST 2017
Hello Aaron Durbin, Furquan Shaikh,
I'd like you to do a code review. Please visit
https://review.coreboot.org/19789
to review the following change.
Change subject: Consolidate reset API, add generic reset_prepare mechanism
......................................................................
Consolidate reset API, add generic reset_prepare mechanism
There are many good reasons why we may want to run some sort of generic
callback before we're executing a reset. Unfortunateley, that is really
hard right now: code that wants to reset simply calls the hard_reset()
function (or one of its ill-differentiated cousins) which is directly
implemented by a myriad of different mainboards, northbridges, SoCs,
etc. More recent x86 SoCs have tried to solve the problem in their own
little corner of soc/intel/common, but it's really something that would
benefit all of coreboot.
This patch expands the concept onto all boards: hard_reset() and friends
get implemented in a generic location where they can run hooks before
calling the platform-specific implementation that is now called
do_hard_reset(). The existing Intel reset_prepare() gets generalized as
soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now
easily be added later if necessary). We will also use this central point
to ensure all platforms flush their cache before reset, which is
generally useful for all cases where we're trying to persist information
in RAM across reboots (like the new persistent CBMEM console does).
Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f
Signed-off-by: Julius Werner <jwerner at chromium.org>
---
M src/include/reset.h
M src/lib/Makefile.inc
A src/lib/reset.c
M src/mainboard/asus/a8v-e_deluxe/romstage.c
M src/mainboard/asus/a8v-e_se/romstage.c
M src/mainboard/asus/k8v-x/romstage.c
M src/mainboard/asus/m2v-mx_se/romstage.c
M src/mainboard/asus/m2v/romstage.c
M src/mainboard/google/cosmos/reset.c
M src/mainboard/google/foster/reset.c
M src/mainboard/google/gale/reset.c
M src/mainboard/google/gru/reset.c
M src/mainboard/google/nyan/reset.c
M src/mainboard/google/nyan_big/reset.c
M src/mainboard/google/nyan_blaze/reset.c
M src/mainboard/google/purin/reset.c
M src/mainboard/google/rotor/reset.c
M src/mainboard/google/smaug/reset.c
M src/mainboard/google/storm/reset.c
M src/mainboard/google/veyron/reset.c
M src/mainboard/google/veyron_mickey/reset.c
M src/mainboard/google/veyron_rialto/reset.c
M src/northbridge/via/cx700/reset.c
M src/northbridge/via/vx900/northbridge.c
M src/soc/dmp/vortex86ex/hard_reset.c
M src/soc/imgtec/pistachio/reset.c
M src/soc/intel/apollolake/reset.c
M src/soc/intel/baytrail/reset.c
M src/soc/intel/broadwell/reset.c
M src/soc/intel/common/reset.c
M src/soc/intel/fsp_baytrail/reset.c
M src/soc/intel/fsp_broadwell_de/reset.c
M src/soc/intel/sch/reset.c
M src/soc/intel/skylake/reset.c
M src/soc/mediatek/mt8173/wdt.c
M src/soc/samsung/exynos5250/power.c
M src/southbridge/amd/agesa/hudson/reset.c
M src/southbridge/amd/amd8111/early_ctrl.c
M src/southbridge/amd/amd8111/reset.c
M src/southbridge/amd/cimx/sb700/reset.c
M src/southbridge/amd/cimx/sb800/reset.c
M src/southbridge/amd/cimx/sb900/reset.c
M src/southbridge/amd/pi/hudson/reset.c
M src/southbridge/amd/sb600/early_setup.c
M src/southbridge/amd/sb600/reset.c
M src/southbridge/amd/sb700/reset.c
M src/southbridge/amd/sb800/early_setup.c
M src/southbridge/amd/sb800/reset.c
M src/southbridge/broadcom/bcm5785/early_setup.c
M src/southbridge/broadcom/bcm5785/reset.c
M src/southbridge/intel/bd82x6x/reset.c
M src/southbridge/intel/fsp_bd82x6x/reset.c
M src/southbridge/intel/fsp_i89xx/reset.c
M src/southbridge/intel/fsp_rangeley/reset.c
M src/southbridge/intel/i3100/reset.c
M src/southbridge/intel/i82801ax/reset.c
M src/southbridge/intel/i82801bx/reset.c
M src/southbridge/intel/i82801dx/reset.c
M src/southbridge/intel/i82801ex/reset.c
M src/southbridge/intel/i82801gx/reset.c
M src/southbridge/intel/lynxpoint/reset.c
M src/southbridge/nvidia/ck804/early_setup.c
M src/southbridge/nvidia/ck804/early_setup_car.c
M src/southbridge/nvidia/ck804/reset.c
M src/southbridge/nvidia/mcp55/early_ctrl.c
M src/southbridge/nvidia/mcp55/reset.c
M src/southbridge/sis/sis966/early_ctrl.c
M src/southbridge/sis/sis966/reset.c
68 files changed, 197 insertions(+), 141 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/19789/1
diff --git a/src/include/reset.h b/src/include/reset.h
index f7501b5..cac853c 100644
--- a/src/include/reset.h
+++ b/src/include/reset.h
@@ -1,15 +1,33 @@
#ifndef RESET_H
#define RESET_H
-#if CONFIG_HAVE_HARD_RESET
-void hard_reset(void);
-#else
-#define hard_reset() do {} while (0)
-#endif
-void soft_reset(void);
-void cpu_reset(void);
+/* Generic reset functions. Call from code that wants to trigger a reset. */
+
+/* Board-level reset. Resets SoC and other components (e.g. TPM). */
+__attribute__((noreturn)) void hard_reset(void);
/* Some Intel SoCs use a special reset that is specific to SoC */
-void global_reset(void);
-/* Some Intel SoCs may need to prepare/wait before reset */
-void reset_prepare(void);
+__attribute__((noreturn)) void global_reset(void);
+/* TODO: come up with clear distinctions for below reset types. */
+__attribute__((noreturn)) void soft_reset(void);
+__attribute__((noreturn)) void cpu_reset(void);
+
+/* Reset implementations. Implement these in SoC or mainboard code. Implement
+ at least hard_reset() if possible, others fall back to it if necessary. */
+void do_hard_reset(void);
+void do_soft_reset(void);
+void do_cpu_reset(void);
+void do_global_reset(void);
+
+enum reset_type { /* listed in order of softness */
+ HARD_RESET,
+ GLOBAL_RESET,
+ SOFT_RESET,
+ CPU_RESET,
+};
+
+/* Callback that an SoC may override to perform special actions before reset.
+ Take into account that softer resets may fall back to harder resets if not
+ implemented... this will *not* trigger another callback! */
+void soc_reset_prepare(enum reset_type reset_type);
+
#endif
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 55f5960..d40b615 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -220,6 +220,13 @@
ramstage-y += halt.c
smm-y += halt.c
+bootblock-y += reset.c
+verstage-y += reset.c
+romstage-y += reset.c
+postcar-y += reset.c
+ramstage-y += reset.c
+smm-y += reset.c
+
postcar-y += bootmode.c
postcar-y += boot_device.c
postcar-y += cbfs.c
diff --git a/src/lib/reset.c b/src/lib/reset.c
new file mode 100644
index 0000000..aafebb7
--- /dev/null
+++ b/src/lib/reset.c
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/cache.h>
+#include <console/console.h>
+#include <halt.h>
+#include <reset.h>
+
+__attribute__((noreturn)) static void __hard_reset(void) {
+ if (IS_ENABLED(CONFIG_HAVE_HARD_RESET))
+ do_hard_reset();
+ else
+ printk(BIOS_CRIT, "No hard_reset implementation, hanging...\n");
+ halt();
+}
+
+/* Not all platforms implement all reset types. Fall back to the next-higher
+ * level of reset by default. */
+__attribute__((weak)) void do_global_reset(void) { __hard_reset(); }
+__attribute__((weak)) void do_soft_reset(void) { do_global_reset(); }
+__attribute__((weak)) void do_cpu_reset(void) { do_soft_reset(); }
+
+__attribute__((weak)) void soc_reset_prepare(enum reset_type rt) { /* no-op */ }
+
+void hard_reset(void)
+{
+ printk(BIOS_INFO, "%s() called!\n", __func__);
+ soc_reset_prepare(HARD_RESET);
+ dcache_clean_all();
+ __hard_reset();
+}
+
+void global_reset(void)
+{
+ printk(BIOS_INFO, "%s() called!\n", __func__);
+ soc_reset_prepare(GLOBAL_RESET);
+ dcache_clean_all();
+ do_global_reset();
+ halt();
+}
+
+void soft_reset(void)
+{
+ printk(BIOS_INFO, "%s() called!\n", __func__);
+ soc_reset_prepare(SOFT_RESET);
+ dcache_clean_all();
+ do_soft_reset();
+ halt();
+}
+
+void cpu_reset(void)
+{
+ printk(BIOS_INFO, "%s() called!\n", __func__);
+ soc_reset_prepare(CPU_RESET);
+ dcache_clean_all();
+ do_cpu_reset();
+ halt();
+}
diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c
index 3601e50..a19b46a 100644
--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c
+++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c
@@ -55,7 +55,7 @@
}
#include <reset.h>
-void soft_reset(void)
+void do_soft_reset(void)
{
uint8_t tmp;
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index fdb8577..706b859 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -55,7 +55,7 @@
}
#include <reset.h>
-void soft_reset(void)
+void do_soft_reset(void)
{
uint8_t tmp;
diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c
index f1477c3..1df033a 100644
--- a/src/mainboard/asus/k8v-x/romstage.c
+++ b/src/mainboard/asus/k8v-x/romstage.c
@@ -53,7 +53,7 @@
}
#include <reset.h>
-void soft_reset(void)
+void do_soft_reset(void)
{
uint8_t tmp;
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index 7864f96..13113b4 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -81,7 +81,7 @@
#include "cpu/amd/model_fxx/fidvid.c"
#include "northbridge/amd/amdk8/resourcemap.c"
-void soft_reset(void)
+void do_soft_reset(void)
{
uint8_t tmp;
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
index 89948b7..61d7488 100644
--- a/src/mainboard/asus/m2v/romstage.c
+++ b/src/mainboard/asus/m2v/romstage.c
@@ -64,7 +64,7 @@
#include "cpu/amd/model_fxx/fidvid.c"
#include "northbridge/amd/amdk8/resourcemap.c"
-void soft_reset(void)
+void do_soft_reset(void)
{
uint8_t tmp;
diff --git a/src/mainboard/google/cosmos/reset.c b/src/mainboard/google/cosmos/reset.c
index e01c741..16ef5f1 100644
--- a/src/mainboard/google/cosmos/reset.c
+++ b/src/mainboard/google/cosmos/reset.c
@@ -15,8 +15,6 @@
#include <reset.h>
-void hard_reset(void)
+void do_hard_reset(void)
{
- while (1)
- ;
}
diff --git a/src/mainboard/google/foster/reset.c b/src/mainboard/google/foster/reset.c
index df16b78..1b9e9e9 100644
--- a/src/mainboard/google/foster/reset.c
+++ b/src/mainboard/google/foster/reset.c
@@ -18,8 +18,7 @@
#include <gpio.h>
#include <reset.h>
-void hard_reset(void)
+void do_hard_reset(void)
{
gpio_output(GPIO(I5), 0);
- while(1);
}
diff --git a/src/mainboard/google/gale/reset.c b/src/mainboard/google/gale/reset.c
index d37051a..23d83bf 100644
--- a/src/mainboard/google/gale/reset.c
+++ b/src/mainboard/google/gale/reset.c
@@ -19,7 +19,7 @@
#include <soc/iomap.h>
#include <reset.h>
-void hard_reset(void)
+void do_hard_reset(void)
{
/*
* At boot time the boot loaders would have set a magic cookie
diff --git a/src/mainboard/google/gru/reset.c b/src/mainboard/google/gru/reset.c
index bd06923..0311d58 100644
--- a/src/mainboard/google/gru/reset.c
+++ b/src/mainboard/google/gru/reset.c
@@ -18,9 +18,7 @@
#include "board.h"
-void hard_reset(void)
+void do_hard_reset(void)
{
gpio_output(GPIO_RESET, 1);
- while (1)
- ;
}
diff --git a/src/mainboard/google/nyan/reset.c b/src/mainboard/google/nyan/reset.c
index 9612d56..ee36292 100644
--- a/src/mainboard/google/nyan/reset.c
+++ b/src/mainboard/google/nyan/reset.c
@@ -17,8 +17,7 @@
#include <gpio.h>
#include <reset.h>
-void hard_reset(void)
+void do_hard_reset(void)
{
gpio_output(GPIO(I5), 0);
- while(1);
}
diff --git a/src/mainboard/google/nyan_big/reset.c b/src/mainboard/google/nyan_big/reset.c
index 9612d56..ee36292 100644
--- a/src/mainboard/google/nyan_big/reset.c
+++ b/src/mainboard/google/nyan_big/reset.c
@@ -17,8 +17,7 @@
#include <gpio.h>
#include <reset.h>
-void hard_reset(void)
+void do_hard_reset(void)
{
gpio_output(GPIO(I5), 0);
- while(1);
}
diff --git a/src/mainboard/google/nyan_blaze/reset.c b/src/mainboard/google/nyan_blaze/reset.c
index 9612d56..ee36292 100644
--- a/src/mainboard/google/nyan_blaze/reset.c
+++ b/src/mainboard/google/nyan_blaze/reset.c
@@ -17,8 +17,7 @@
#include <gpio.h>
#include <reset.h>
-void hard_reset(void)
+void do_hard_reset(void)
{
gpio_output(GPIO(I5), 0);
- while(1);
}
diff --git a/src/mainboard/google/purin/reset.c b/src/mainboard/google/purin/reset.c
index 5497175..3667bbf 100644
--- a/src/mainboard/google/purin/reset.c
+++ b/src/mainboard/google/purin/reset.c
@@ -15,8 +15,6 @@
#include <reset.h>
-void hard_reset(void)
+void do_hard_reset(void)
{
- while (1)
- ;
}
diff --git a/src/mainboard/google/rotor/reset.c b/src/mainboard/google/rotor/reset.c
index 37c2db7..fc97f2d 100644
--- a/src/mainboard/google/rotor/reset.c
+++ b/src/mainboard/google/rotor/reset.c
@@ -16,7 +16,7 @@
#include <reset.h>
#include <soc/reset.h>
-void hard_reset(void)
+void do_hard_reset(void)
{
mvmap2315_reset();
}
diff --git a/src/mainboard/google/smaug/reset.c b/src/mainboard/google/smaug/reset.c
index f875829..fc9a0b6 100644
--- a/src/mainboard/google/smaug/reset.c
+++ b/src/mainboard/google/smaug/reset.c
@@ -18,9 +18,7 @@
#include "gpio.h"
-void hard_reset(void)
+void do_hard_reset(void)
{
gpio_output(AP_SYS_RESET_L, 0);
- while (1)
- ;
}
diff --git a/src/mainboard/google/storm/reset.c b/src/mainboard/google/storm/reset.c
index 94dcd4b..d8f2527 100644
--- a/src/mainboard/google/storm/reset.c
+++ b/src/mainboard/google/storm/reset.c
@@ -37,12 +37,9 @@
write32(APCS_WDT0_BITE_TIME, RESET_WDT_BITE_TIME);
write32(APCS_WDT0_EN, 1);
write32(APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE, 1);
-
- for (;;)
- ;
}
-void hard_reset(void)
+void do_hard_reset(void)
{
wdog_reset();
}
diff --git a/src/mainboard/google/veyron/reset.c b/src/mainboard/google/veyron/reset.c
index 0d11e76..a937aff 100644
--- a/src/mainboard/google/veyron/reset.c
+++ b/src/mainboard/google/veyron/reset.c
@@ -19,8 +19,7 @@
#include "board.h"
-void hard_reset(void)
+void do_hard_reset(void)
{
gpio_output(GPIO_RESET, 1);
- while (1);
}
diff --git a/src/mainboard/google/veyron_mickey/reset.c b/src/mainboard/google/veyron_mickey/reset.c
index 0d11e76..a937aff 100644
--- a/src/mainboard/google/veyron_mickey/reset.c
+++ b/src/mainboard/google/veyron_mickey/reset.c
@@ -19,8 +19,7 @@
#include "board.h"
-void hard_reset(void)
+void do_hard_reset(void)
{
gpio_output(GPIO_RESET, 1);
- while (1);
}
diff --git a/src/mainboard/google/veyron_rialto/reset.c b/src/mainboard/google/veyron_rialto/reset.c
index cf3a6d8..a937aff 100644
--- a/src/mainboard/google/veyron_rialto/reset.c
+++ b/src/mainboard/google/veyron_rialto/reset.c
@@ -19,9 +19,7 @@
#include "board.h"
-void hard_reset(void)
+void do_hard_reset(void)
{
gpio_output(GPIO_RESET, 1);
- while (1)
- ;
}
diff --git a/src/northbridge/via/cx700/reset.c b/src/northbridge/via/cx700/reset.c
index b3c2a65..8a62759 100644
--- a/src/northbridge/via/cx700/reset.c
+++ b/src/northbridge/via/cx700/reset.c
@@ -16,7 +16,7 @@
#include <arch/io.h>
#include <reset.h>
-void hard_reset(void)
+void do_hard_reset(void)
{
outb((1 << 2) | (1 << 1), 0xcf9);
}
diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c
index 7429c4f..5aa1d7d 100644
--- a/src/northbridge/via/vx900/northbridge.c
+++ b/src/northbridge/via/vx900/northbridge.c
@@ -43,7 +43,7 @@
* remapping mechanism will overflow, the effects of which are unknown.
*/
-void hard_reset(void)
+void do_hard_reset(void)
{
outb((1 << 2) | (1 << 1), 0xcf9);
}
diff --git a/src/soc/dmp/vortex86ex/hard_reset.c b/src/soc/dmp/vortex86ex/hard_reset.c
index 9b9c426..fe127aa 100644
--- a/src/soc/dmp/vortex86ex/hard_reset.c
+++ b/src/soc/dmp/vortex86ex/hard_reset.c
@@ -16,6 +16,6 @@
#include <arch/io.h>
#include <reset.h>
-void hard_reset(void)
+void do_hard_reset(void)
{
}
diff --git a/src/soc/imgtec/pistachio/reset.c b/src/soc/imgtec/pistachio/reset.c
index fc581df..c0e9105 100644
--- a/src/soc/imgtec/pistachio/reset.c
+++ b/src/soc/imgtec/pistachio/reset.c
@@ -20,7 +20,7 @@
#define PISTACHIO_WD_ADDR 0xB8102100
#define PISTACHIO_WD_SW_RST_OFFSET 0x0000
-void hard_reset(void)
+void do_hard_reset(void)
{
/* Generate system reset */
write32(PISTACHIO_WD_ADDR + PISTACHIO_WD_SW_RST_OFFSET, 0x1);
diff --git a/src/soc/intel/apollolake/reset.c b/src/soc/intel/apollolake/reset.c
index 56273cc..15e78fe 100644
--- a/src/soc/intel/apollolake/reset.c
+++ b/src/soc/intel/apollolake/reset.c
@@ -23,13 +23,13 @@
#define CSE_WAIT_MAX_MS 1000
-void global_reset(void)
+void do_global_reset(void)
{
global_reset_enable(1);
- hard_reset();
+ do_hard_reset();
}
-void reset_prepare(void)
+void soc_reset_prepare(enum reset_type reset_type)
{
struct stopwatch sw;
diff --git a/src/soc/intel/baytrail/reset.c b/src/soc/intel/baytrail/reset.c
index fd38f61..e38a2e6 100644
--- a/src/soc/intel/baytrail/reset.c
+++ b/src/soc/intel/baytrail/reset.c
@@ -29,13 +29,13 @@
outb(RST_CPU | SYS_RST, RST_CNT);
}
-void soft_reset(void)
+void do_soft_reset(void)
{
/* Sends INIT# to CPU */
outb(RST_CPU, RST_CNT);
}
-void hard_reset(void)
+void do_hard_reset(void)
{
/* Don't power cycle on hard_reset(). It's not really clear what the
* semantics should be for the meaning of hard_reset(). */
diff --git a/src/soc/intel/broadwell/reset.c b/src/soc/intel/broadwell/reset.c
index e4d01c2..ad90dcd 100644
--- a/src/soc/intel/broadwell/reset.c
+++ b/src/soc/intel/broadwell/reset.c
@@ -28,12 +28,12 @@
* with ETR[20] set.
*/
-void soft_reset(void)
+void do_soft_reset(void)
{
outb(0x04, 0xcf9);
}
-void hard_reset(void)
+void do_hard_reset(void)
{
outb(0x06, 0xcf9);
}
diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c
index e9be185..ea9b7f1 100644
--- a/src/soc/intel/common/reset.c
+++ b/src/soc/intel/common/reset.c
@@ -25,39 +25,22 @@
#define RST_CPU (1 << 2)
#define SYS_RST (1 << 1)
-#ifdef __ROMCC__
-#define WEAK
-#else
-#define WEAK __attribute__((weak))
-#endif
-
-void WEAK reset_prepare(void) { /* do nothing */ }
-
#if IS_ENABLED(CONFIG_HAVE_HARD_RESET)
-void hard_reset(void)
+void do_hard_reset(void)
{
- reset_prepare();
/* S0->S5->S0 trip. */
outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT);
- while (1)
- hlt();
}
#endif
-void soft_reset(void)
+void do_soft_reset(void)
{
- reset_prepare();
/* PMC_PLTRST# asserted. */
outb(RST_CPU | SYS_RST, RST_CNT);
- while (1)
- hlt();
}
-void cpu_reset(void)
+void do_cpu_reset(void)
{
- reset_prepare();
/* Sends INIT# to CPU */
outb(RST_CPU, RST_CNT);
- while (1)
- hlt();
}
diff --git a/src/soc/intel/fsp_baytrail/reset.c b/src/soc/intel/fsp_baytrail/reset.c
index fd38f61..e38a2e6 100644
--- a/src/soc/intel/fsp_baytrail/reset.c
+++ b/src/soc/intel/fsp_baytrail/reset.c
@@ -29,13 +29,13 @@
outb(RST_CPU | SYS_RST, RST_CNT);
}
-void soft_reset(void)
+void do_soft_reset(void)
{
/* Sends INIT# to CPU */
outb(RST_CPU, RST_CNT);
}
-void hard_reset(void)
+void do_hard_reset(void)
{
/* Don't power cycle on hard_reset(). It's not really clear what the
* semantics should be for the meaning of hard_reset(). */
diff --git a/src/soc/intel/fsp_broadwell_de/reset.c b/src/soc/intel/fsp_broadwell_de/reset.c
index 7e1c582..78d7493 100644
--- a/src/soc/intel/fsp_broadwell_de/reset.c
+++ b/src/soc/intel/fsp_broadwell_de/reset.c
@@ -23,7 +23,7 @@
outb(0x06, 0xcf9);
}
-void hard_reset(void)
+void do_hard_reset(void)
{
warm_reset();
}
diff --git a/src/soc/intel/sch/reset.c b/src/soc/intel/sch/reset.c
index 2574565..91bcd69 100644
--- a/src/soc/intel/sch/reset.c
+++ b/src/soc/intel/sch/reset.c
@@ -17,12 +17,12 @@
#include <arch/io.h>
#include <reset.h>
-void soft_reset(void)
+void do_soft_reset(void)
{
outb(0x04, 0xcf9);
}
-void hard_reset(void)
+void do_hard_reset(void)
{
outb(0x02, 0xcf9);
outb(0x06, 0xcf9);
diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c
index 6910914..dee98a4 100644
--- a/src/soc/intel/skylake/reset.c
+++ b/src/soc/intel/skylake/reset.c
@@ -41,7 +41,7 @@
hard_reset();
}
-void global_reset(void)
+void do_global_reset(void)
{
if (send_global_reset() != 0) {
/* If ME unable to reset platform then
diff --git a/src/soc/mediatek/mt8173/wdt.c b/src/soc/mediatek/mt8173/wdt.c
index 93ffe09..22f1c87 100644
--- a/src/soc/mediatek/mt8173/wdt.c
+++ b/src/soc/mediatek/mt8173/wdt.c
@@ -57,10 +57,7 @@
return wdt_sta;
}
-void hard_reset(void)
+void do_hard_reset(void)
{
write32(&mt8173_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
-
- while (1)
- ;
}
diff --git a/src/soc/samsung/exynos5250/power.c b/src/soc/samsung/exynos5250/power.c
index f27650d..de99a82 100644
--- a/src/soc/samsung/exynos5250/power.c
+++ b/src/soc/samsung/exynos5250/power.c
@@ -39,7 +39,7 @@
setbits_le32(&exynos_power->sw_reset, 1);
}
-void hard_reset(void)
+void do_hard_reset(void)
{
power_reset();
}
diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c
index 200ec14..e3f36f3 100644
--- a/src/southbridge/amd/agesa/hudson/reset.c
+++ b/src/southbridge/amd/agesa/hudson/reset.c
@@ -21,7 +21,7 @@
#include <northbridge/amd/amdk8/reset_test.c>
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c
index f451003..2161669 100644
--- a/src/southbridge/amd/amd8111/early_ctrl.c
+++ b/src/southbridge/amd/amd8111/early_ctrl.c
@@ -38,7 +38,7 @@
enable_cf9_x(sbbusn, sbdn);
}
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
/* reset */
@@ -71,7 +71,7 @@
}
-void soft_reset(void)
+void do_soft_reset(void)
{
unsigned sblk = get_sblk();
diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c
index fd2c82a..fea8891 100644
--- a/src/southbridge/amd/amd8111/reset.c
+++ b/src/southbridge/amd/amd8111/reset.c
@@ -37,7 +37,7 @@
#include "../../../northbridge/amd/amdk8/reset_test.c"
-void hard_reset(void)
+void do_hard_reset(void)
{
pci_devfn_t dev;
unsigned bus;
diff --git a/src/southbridge/amd/cimx/sb700/reset.c b/src/southbridge/amd/cimx/sb700/reset.c
index a5c42b7..40e861c 100644
--- a/src/southbridge/amd/cimx/sb700/reset.c
+++ b/src/southbridge/amd/cimx/sb700/reset.c
@@ -40,7 +40,7 @@
}
}
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
@@ -50,7 +50,7 @@
}
//SbReset();
-void soft_reset(void)
+void do_soft_reset(void)
{
set_bios_reset();
/* link reset */
diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c
index a5c42b7..40e861c 100644
--- a/src/southbridge/amd/cimx/sb800/reset.c
+++ b/src/southbridge/amd/cimx/sb800/reset.c
@@ -40,7 +40,7 @@
}
}
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
@@ -50,7 +50,7 @@
}
//SbReset();
-void soft_reset(void)
+void do_soft_reset(void)
{
set_bios_reset();
/* link reset */
diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c
index a5c42b7..40e861c 100644
--- a/src/southbridge/amd/cimx/sb900/reset.c
+++ b/src/southbridge/amd/cimx/sb900/reset.c
@@ -40,7 +40,7 @@
}
}
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
@@ -50,7 +50,7 @@
}
//SbReset();
-void soft_reset(void)
+void do_soft_reset(void)
{
set_bios_reset();
/* link reset */
diff --git a/src/southbridge/amd/pi/hudson/reset.c b/src/southbridge/amd/pi/hudson/reset.c
index 200ec14..e3f36f3 100644
--- a/src/southbridge/amd/pi/hudson/reset.c
+++ b/src/southbridge/amd/pi/hudson/reset.c
@@ -21,7 +21,7 @@
#include <northbridge/amd/amdk8/reset_test.c>
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c
index 2445310..f68bfd5 100644
--- a/src/southbridge/amd/sb600/early_setup.c
+++ b/src/southbridge/amd/sb600/early_setup.c
@@ -173,7 +173,7 @@
}
}
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
@@ -182,7 +182,7 @@
outb(0x0e, 0x0cf9);
}
-void soft_reset(void)
+void do_soft_reset(void)
{
set_bios_reset();
/* link reset */
diff --git a/src/southbridge/amd/sb600/reset.c b/src/southbridge/amd/sb600/reset.c
index beb35d1..04bf3f4 100644
--- a/src/southbridge/amd/sb600/reset.c
+++ b/src/southbridge/amd/sb600/reset.c
@@ -21,7 +21,7 @@
#include <northbridge/amd/amdk8/reset_test.c>
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c
index 3c44982..0878039 100644
--- a/src/southbridge/amd/sb700/reset.c
+++ b/src/southbridge/amd/sb700/reset.c
@@ -44,7 +44,7 @@
}
}
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
@@ -56,7 +56,7 @@
outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
}
-void soft_reset(void)
+void do_soft_reset(void)
{
set_bios_reset();
/* link reset */
diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
index 7ac6ec8..33422d9 100644
--- a/src/southbridge/amd/sb800/early_setup.c
+++ b/src/southbridge/amd/sb800/early_setup.c
@@ -220,7 +220,7 @@
pmio_write(0x81, byte);
}
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
@@ -229,7 +229,7 @@
outb(0x0e, 0x0cf9);
}
-void soft_reset(void)
+void do_soft_reset(void)
{
set_bios_reset();
/* link reset */
diff --git a/src/southbridge/amd/sb800/reset.c b/src/southbridge/amd/sb800/reset.c
index 200ec14..e3f36f3 100644
--- a/src/southbridge/amd/sb800/reset.c
+++ b/src/southbridge/amd/sb800/reset.c
@@ -21,7 +21,7 @@
#include <northbridge/amd/amdk8/reset_test.c>
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c
index 6ee4f6b..7235444 100644
--- a/src/southbridge/broadcom/bcm5785/early_setup.c
+++ b/src/southbridge/broadcom/bcm5785/early_setup.c
@@ -105,7 +105,7 @@
}
-void hard_reset(void)
+void do_hard_reset(void)
{
bcm5785_enable_wdt_port_cf9();
@@ -116,7 +116,7 @@
outb(0x0e, 0x0cf9);
}
-void soft_reset(void)
+void do_soft_reset(void)
{
bcm5785_enable_wdt_port_cf9();
diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c
index 7511d29..1041aae 100644
--- a/src/southbridge/broadcom/bcm5785/reset.c
+++ b/src/southbridge/broadcom/bcm5785/reset.c
@@ -21,7 +21,7 @@
#include "../../../northbridge/amd/amdk8/reset_test.c"
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
diff --git a/src/southbridge/intel/bd82x6x/reset.c b/src/southbridge/intel/bd82x6x/reset.c
index 804fb81..7faadb6 100644
--- a/src/southbridge/intel/bd82x6x/reset.c
+++ b/src/southbridge/intel/bd82x6x/reset.c
@@ -17,12 +17,12 @@
#include <arch/io.h>
#include <reset.h>
-void soft_reset(void)
+void do_soft_reset(void)
{
outb(0x04, 0xcf9);
}
-void hard_reset(void)
+void do_hard_reset(void)
{
outb(0x06, 0xcf9);
}
diff --git a/src/southbridge/intel/fsp_bd82x6x/reset.c b/src/southbridge/intel/fsp_bd82x6x/reset.c
index a2e8236..b1468da 100644
--- a/src/southbridge/intel/fsp_bd82x6x/reset.c
+++ b/src/southbridge/intel/fsp_bd82x6x/reset.c
@@ -18,12 +18,12 @@
#include <arch/io.h>
#include <reset.h>
-void soft_reset(void)
+void do_soft_reset(void)
{
outb(0x04, 0xcf9);
}
-void hard_reset(void)
+void do_hard_reset(void)
{
outb(0x06, 0xcf9);
}
diff --git a/src/southbridge/intel/fsp_i89xx/reset.c b/src/southbridge/intel/fsp_i89xx/reset.c
index a2e8236..b1468da 100644
--- a/src/southbridge/intel/fsp_i89xx/reset.c
+++ b/src/southbridge/intel/fsp_i89xx/reset.c
@@ -18,12 +18,12 @@
#include <arch/io.h>
#include <reset.h>
-void soft_reset(void)
+void do_soft_reset(void)
{
outb(0x04, 0xcf9);
}
-void hard_reset(void)
+void do_hard_reset(void)
{
outb(0x06, 0xcf9);
}
diff --git a/src/southbridge/intel/fsp_rangeley/reset.c b/src/southbridge/intel/fsp_rangeley/reset.c
index 298dbce..10b82ff 100644
--- a/src/southbridge/intel/fsp_rangeley/reset.c
+++ b/src/southbridge/intel/fsp_rangeley/reset.c
@@ -18,12 +18,12 @@
#include <arch/io.h>
#include <reset.h>
-void soft_reset(void)
+void do_soft_reset(void)
{
hard_reset();
}
-void hard_reset(void)
+void do_hard_reset(void)
{
outb(0x02, 0xcf9);
outb(0x06, 0xcf9);
diff --git a/src/southbridge/intel/i3100/reset.c b/src/southbridge/intel/i3100/reset.c
index 595bed3..af000e3 100644
--- a/src/southbridge/intel/i3100/reset.c
+++ b/src/southbridge/intel/i3100/reset.c
@@ -17,7 +17,7 @@
#include <arch/io.h>
#include <reset.h>
-void hard_reset(void)
+void do_hard_reset(void)
{
outb(0x06, 0xcf9);
}
diff --git a/src/southbridge/intel/i82801ax/reset.c b/src/southbridge/intel/i82801ax/reset.c
index 74be595..25254ca 100644
--- a/src/southbridge/intel/i82801ax/reset.c
+++ b/src/southbridge/intel/i82801ax/reset.c
@@ -17,7 +17,7 @@
#include <reset.h>
#include <arch/io.h>
-void hard_reset(void)
+void do_hard_reset(void)
{
/* Try rebooting through port 0xcf9. */
outb((1 << 2) | (1 << 1), 0xcf9);
diff --git a/src/southbridge/intel/i82801bx/reset.c b/src/southbridge/intel/i82801bx/reset.c
index 4a82b35..41b99c7 100644
--- a/src/southbridge/intel/i82801bx/reset.c
+++ b/src/southbridge/intel/i82801bx/reset.c
@@ -17,7 +17,7 @@
#include <arch/io.h>
#include <reset.h>
-void hard_reset(void)
+void do_hard_reset(void)
{
/* Try rebooting through port 0xcf9. */
outb((1 << 2) | (1 << 1), 0xcf9);
diff --git a/src/southbridge/intel/i82801dx/reset.c b/src/southbridge/intel/i82801dx/reset.c
index a6db91c..1839ad6 100644
--- a/src/southbridge/intel/i82801dx/reset.c
+++ b/src/southbridge/intel/i82801dx/reset.c
@@ -16,7 +16,7 @@
#include <arch/io.h>
#include <reset.h>
-void hard_reset(void)
+void do_hard_reset(void)
{
/* Try rebooting through port 0xcf9 */
outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
diff --git a/src/southbridge/intel/i82801ex/reset.c b/src/southbridge/intel/i82801ex/reset.c
index 8036ffd..10ba4ba 100644
--- a/src/southbridge/intel/i82801ex/reset.c
+++ b/src/southbridge/intel/i82801ex/reset.c
@@ -1,7 +1,7 @@
#include <arch/io.h>
#include <reset.h>
-void hard_reset(void)
+void do_hard_reset(void)
{
/* Try rebooting through port 0xcf9 */
outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
diff --git a/src/southbridge/intel/i82801gx/reset.c b/src/southbridge/intel/i82801gx/reset.c
index 97b8225..e18f3e8 100644
--- a/src/southbridge/intel/i82801gx/reset.c
+++ b/src/southbridge/intel/i82801gx/reset.c
@@ -17,20 +17,20 @@
#include <arch/io.h>
#include <reset.h>
-void soft_reset(void)
+void do_soft_reset(void)
{
outb(0x04, 0xcf9);
}
#if 0
-void hard_reset(void)
+void do_hard_reset(void)
{
/* Try rebooting through port 0xcf9. */
outb((1 << 2) | (1 << 1), 0xcf9);
}
#endif
-void hard_reset(void)
+void do_hard_reset(void)
{
outb(0x02, 0xcf9);
outb(0x06, 0xcf9);
diff --git a/src/southbridge/intel/lynxpoint/reset.c b/src/southbridge/intel/lynxpoint/reset.c
index 804fb81..7faadb6 100644
--- a/src/southbridge/intel/lynxpoint/reset.c
+++ b/src/southbridge/intel/lynxpoint/reset.c
@@ -17,12 +17,12 @@
#include <arch/io.h>
#include <reset.h>
-void soft_reset(void)
+void do_soft_reset(void)
{
outb(0x04, 0xcf9);
}
-void hard_reset(void)
+void do_hard_reset(void)
{
outb(0x06, 0xcf9);
}
diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c
index 1d4999c..79c9eff 100644
--- a/src/southbridge/nvidia/ck804/early_setup.c
+++ b/src/southbridge/nvidia/ck804/early_setup.c
@@ -310,7 +310,7 @@
return set_ht_link_ck804(4);
}
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
@@ -319,7 +319,7 @@
outb(0x0e, 0x0cf9);
}
-void soft_reset(void)
+void do_soft_reset(void)
{
set_bios_reset();
diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c
index 689f989..aeea41b 100644
--- a/src/southbridge/nvidia/ck804/early_setup_car.c
+++ b/src/southbridge/nvidia/ck804/early_setup_car.c
@@ -357,7 +357,7 @@
return set_ht_link_ck804(4);
}
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
@@ -366,7 +366,7 @@
outb(0x0e, 0x0cf9);
}
-void soft_reset(void)
+void do_soft_reset(void)
{
set_bios_reset();
diff --git a/src/southbridge/nvidia/ck804/reset.c b/src/southbridge/nvidia/ck804/reset.c
index ad994de..bcb6dfc 100644
--- a/src/southbridge/nvidia/ck804/reset.c
+++ b/src/southbridge/nvidia/ck804/reset.c
@@ -21,7 +21,7 @@
#include "../../../northbridge/amd/amdk8/reset_test.c"
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9. */
diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c
index 1f80316..cb3e2f0 100644
--- a/src/southbridge/nvidia/mcp55/early_ctrl.c
+++ b/src/southbridge/nvidia/mcp55/early_ctrl.c
@@ -25,7 +25,7 @@
#endif
#include "mcp55.h"
-void soft_reset(void)
+void do_soft_reset(void)
{
set_bios_reset();
/* link reset */
@@ -33,7 +33,7 @@
outb(0x06, 0x0cf9);
}
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
diff --git a/src/southbridge/nvidia/mcp55/reset.c b/src/southbridge/nvidia/mcp55/reset.c
index a381cd3..7be98d7 100644
--- a/src/southbridge/nvidia/mcp55/reset.c
+++ b/src/southbridge/nvidia/mcp55/reset.c
@@ -24,7 +24,7 @@
#include "../../../northbridge/amd/amdk8/reset_test.c"
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
diff --git a/src/southbridge/sis/sis966/early_ctrl.c b/src/southbridge/sis/sis966/early_ctrl.c
index 74ae1fa..4fb2d9d 100644
--- a/src/southbridge/sis/sis966/early_ctrl.c
+++ b/src/southbridge/sis/sis966/early_ctrl.c
@@ -29,7 +29,7 @@
return (dev>>15) & 0x1f;
}
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
@@ -44,7 +44,7 @@
/* set VFSMAF ( VID/FID System Management Action Field) to 2 */
}
-void soft_reset(void)
+void do_soft_reset(void)
{
set_bios_reset();
diff --git a/src/southbridge/sis/sis966/reset.c b/src/southbridge/sis/sis966/reset.c
index a381cd3..7be98d7 100644
--- a/src/southbridge/sis/sis966/reset.c
+++ b/src/southbridge/sis/sis966/reset.c
@@ -24,7 +24,7 @@
#include "../../../northbridge/amd/amdk8/reset_test.c"
-void hard_reset(void)
+void do_hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
--
To view, visit https://review.coreboot.org/19789
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Julius Werner <jwerner at chromium.org>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
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