[coreboot-gerrit] Change in coreboot[master]: rockchip/rk3399: soc: resize reserve memory

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/19431 )

Change subject: rockchip/rk3399: soc: resize reserve memory
......................................................................


rockchip/rk3399: soc: resize reserve memory

Reserve the whole TZRAM area because it will be marked as secure-only
by BL31 and can not be accessed by the non-secure kernel.

CQ-DEPEND=CL:452659
BUG=chrome-os-partner:57361
BRANCH=firmware-gru-8785.B
TEST=the reserve memory is resized

Change-Id: Ie3ab39598f3f7cb96feb0c574e230e7fcb53a1a4
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: f34d254e1dfc9ae95a784aba22503e75a2fa65f1
Original-Change-Id: I39c4cb530f41a7b0f7f3064125072dd85b62276f
Original-Signed-off-by: Xing Zheng <zhengxing at rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/418102
Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
Original-(cherry picked from commit ea9fe064a9b1e1ce81fca74f829a0fb6e78ce426)
Original-Reviewed-on: https://chromium-review.googlesource.com/452640
Original-Tested-by: Julius Werner <jwerner at chromium.org>
Original-Commit-Queue: Julius Werner <jwerner at chromium.org>
Reviewed-on: https://review.coreboot.org/19431
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Julius Werner <jwerner at chromium.org>
---
M src/soc/rockchip/rk3399/soc.c
1 file changed, 5 insertions(+), 3 deletions(-)

Approvals:
  Julius Werner: Looks good to me, approved
  build bot (Jenkins): Verified



diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c
index 4418a27..37de652 100644
--- a/src/soc/rockchip/rk3399/soc.c
+++ b/src/soc/rockchip/rk3399/soc.c
@@ -25,6 +25,7 @@
 #include <stdlib.h>
 #include <string.h>
 #include <symbols.h>
+#include <arm-trusted-firmware/plat/rockchip/rk3399/include/shared/bl31_param.h>
 
 static void soc_read_resources(device_t dev)
 {
@@ -33,10 +34,11 @@
 
 static void soc_init(device_t dev)
 {
-	/* reserve bl31 image, which define in
-	 * arm-trusted-firmware/plat/rockchip/rk3399/include/platform_def.h
+	/*
+	 * Reserve the whole TZRAM area because it will be marked as secure-only
+	 * by BL31 and can not be accessed by the non-secure kernel.
 	 */
-	mmio_resource(dev, 1, (0x10000 / KiB), (0x80000 / KiB));
+	mmio_resource(dev, 1, (TZRAM_BASE / KiB), (TZRAM_SIZE / KiB));
 
 	if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) && display_init_required())
 		rk_display_init(dev);

-- 
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Gerrit-MessageType: merged
Gerrit-Change-Id: Ie3ab39598f3f7cb96feb0c574e230e7fcb53a1a4
Gerrit-PatchSet: 4
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: Julius Werner <jwerner at chromium.org>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>