[coreboot-gerrit] Change in coreboot[master]: WIP soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCK
Marshall Dawson (Code Review)
gerrit at coreboot.org
Thu May 18 01:43:41 CEST 2017
Marshall Dawson has uploaded a new change for review. ( https://review.coreboot.org/19755 )
Change subject: WIP soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCK
......................................................................
WIP soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCK
Add dedicated CAR setup and teardown functions and, Kconfig
options to force their inclusion into the build. The .S files
are effectively duplicated code from the cache_as_ram.inc file.
The .S files use global proc names in anticipation for use with
the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE.
Move the mainboard romstage functionality into the soc directory
and change the function name to be compatible with the call
from assembly_entry.S.
Move InitReset and InitEarly to bootblock. These AGESA entry
points set some default settings, and release/recapture the
AP cores.
todo:
* clean up BioCallouts.c file
* preserve BIST
* look for ways to refactor to further clean up files used
in bootblock?
Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/cpu/x86/lapic/Makefile.inc
M src/mainboard/amd/gardenia/BiosCallOuts.c
M src/mainboard/amd/gardenia/Makefile.inc
M src/mainboard/amd/gardenia/romstage.c
M src/soc/amd/common/Makefile.inc
A src/soc/amd/common/block/cpu/Kconfig
A src/soc/amd/common/block/cpu/Makefile.inc
A src/soc/amd/common/block/cpu/car/cache_as_ram.S
A src/soc/amd/common/block/cpu/car/exit_car.S
M src/soc/amd/stoneyridge/Kconfig
M src/soc/amd/stoneyridge/Makefile.inc
A src/soc/amd/stoneyridge/bootblock.c
M src/soc/amd/stoneyridge/include/soc/northbridge.h
A src/soc/amd/stoneyridge/romstage.c
M src/vendorcode/amd/pi/Makefile.inc
15 files changed, 366 insertions(+), 68 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/19755/1
diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc
index 9df2c5f..1525521 100644
--- a/src/cpu/x86/lapic/Makefile.inc
+++ b/src/cpu/x86/lapic/Makefile.inc
@@ -1,6 +1,7 @@
ramstage-y += lapic.c
ramstage-y += lapic_cpu_init.c
ramstage-y += secondary.S
+bootblock-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
bootblock-y += boot_cpu.c
diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c
index 7ff4eb8..a494512 100644
--- a/src/mainboard/amd/gardenia/BiosCallOuts.c
+++ b/src/mainboard/amd/gardenia/BiosCallOuts.c
@@ -31,6 +31,7 @@
#include "BiosCallOuts.h"
#include "northbridge/amd/pi/dimmSpd.h"
#include "northbridge/amd/pi/agesawrapper.h"
+#include <rules.h>
static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);
@@ -39,7 +40,11 @@
{AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
{AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
{AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
+#if ENV_BOOTBLOCK
+ {AGESA_READ_SPD, agesa_NoopUnsupported },
+#else
{AGESA_READ_SPD, agesa_ReadSpd },
+#endif
{AGESA_DO_RESET, agesa_Reset },
{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
@@ -92,6 +97,9 @@
FchParams_reset->FchReset.SataEnable = hudson_sata_enable();
FchParams_reset->FchReset.IdeEnable = hudson_ide_enable();
FchParams_reset->EarlyOemGpioTable = oem_gardenia_gpio;
+#if ENV_BOOTBLOCK
+ }
+#else
} else if (StdHeader->Func == AMD_INIT_ENV) {
FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
@@ -124,6 +132,7 @@
break;
}
}
+#endif /* ENV_BOOTBLOCK */
printk(BIOS_DEBUG, "Done\n");
return AGESA_SUCCESS;
diff --git a/src/mainboard/amd/gardenia/Makefile.inc b/src/mainboard/amd/gardenia/Makefile.inc
index ba5e377..de24187 100644
--- a/src/mainboard/amd/gardenia/Makefile.inc
+++ b/src/mainboard/amd/gardenia/Makefile.inc
@@ -13,6 +13,9 @@
# GNU General Public License for more details.
#
+bootblock-y += BiosCallOuts.c
+bootblock-y += OemCustomize.c
+
romstage-y += BiosCallOuts.c
romstage-y += OemCustomize.c
diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c
index 788d3d7..e25adbd 100644
--- a/src/mainboard/amd/gardenia/romstage.c
+++ b/src/mainboard/amd/gardenia/romstage.c
@@ -13,70 +13,3 @@
* GNU General Public License for more details.
*/
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <cbmem.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/x86/bist.h>
-#include <cpu/amd/car.h>
-#include <northbridge/amd/pi/agesawrapper.h>
-#include <northbridge/amd/pi/agesawrapper_call.h>
-#include <soc/hudson.h>
-#include <amdblocks/psp.h>
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- u32 val;
-
- amd_initmmio();
- hudson_lpc_port80();
- hudson_lpc_decode();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
-
-#if IS_ENABLED(CONFIG_STONEYRIDGE_UART)
- configure_hudson_uart();
-#endif
- post_code(0x31);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist & 0x7FFFFFFF); /* Mask bit 31. One result of Silicon Observation */
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- post_code(0x37);
- AGESAWRAPPER(amdinitreset);
- post_code(0x38);
- printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n");
-
- post_code(0x39);
- AGESAWRAPPER(amdinitearly);
-
- post_code(0x40);
- AGESAWRAPPER(amdinitpost);
-
- post_code(0x41);
- psp_notify_dram();
-
- post_code(0x42);
- cbmem_initialize_empty();
-
- post_code(0x43);
- AGESAWRAPPER(amdinitenv);
- /* TODO: Disable cache is not ok. */
- disable_cache_as_ram();
-
- post_code(0x50);
- copy_and_run();
-
- post_code(0x54); /* Should never see this post code. */
-}
diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc
index 570dab3..fe87504 100644
--- a/src/soc/amd/common/Makefile.inc
+++ b/src/soc/amd/common/Makefile.inc
@@ -1,6 +1,18 @@
ifeq ($(CONFIG_SOC_AMD_COMMON),y)
+subdirs-y += block/
+
+ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y)
+
+bootblock-y += agesawrapper.c
+bootblock-y += def_callouts.c
+bootblock-y += heapmanager.c
+
+else # ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y)
+
cpu_incs-y += $(src)/soc/amd/common/cache_as_ram.inc
+
+endif # ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y)
romstage-y += agesawrapper.c
romstage-y += def_callouts.c
@@ -13,6 +25,6 @@
ramstage-y += heapmanager.c
ramstage-$(CONFIG_SPI_FLASH) += spi.c
-subdirs-y += ./*
+subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK) += ./block
endif
diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig
new file mode 100644
index 0000000..d301eb3
--- /dev/null
+++ b/src/soc/amd/common/block/cpu/Kconfig
@@ -0,0 +1,5 @@
+config SOC_AMD_COMMON_BLOCK_CAR
+ bool
+ default n
+ help
+ This option allows you to select how cache-as-ram (CAR) is set up.
diff --git a/src/soc/amd/common/block/cpu/Makefile.inc b/src/soc/amd/common/block/cpu/Makefile.inc
new file mode 100644
index 0000000..8e6972e
--- /dev/null
+++ b/src/soc/amd/common/block/cpu/Makefile.inc
@@ -0,0 +1,2 @@
+bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/cache_as_ram.S
+romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/exit_car.S
diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
new file mode 100644
index 0000000..6c42a99
--- /dev/null
+++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
@@ -0,0 +1,140 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/******************************************************************************
+ * AMD Generic Encapsulated Software Architecture
+ *
+ * $Workfile:: cache_as_ram.inc
+ *
+ * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier
+ *
+ ******************************************************************************
+ */
+
+#include "gcccar.inc"
+#include <cpu/x86/cache.h>
+#include <cpu/x86/post_code.h>
+
+/*
+ * XMM map:
+ * xmm0: BIST
+ * xmm1: backup ebx -- cpu_init_detected
+ */
+
+.global bootblock_pre_c_entry
+bootblock_pre_c_entry:
+
+ post_code(0xa0)
+
+ /* enable SSE2 128bit instructions */
+ /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
+
+ movl %cr4, %eax
+ orl $(3<<9), %eax
+ movl %eax, %cr4
+
+ /* Get the cpu_init_detected */
+ mov $1, %eax
+ cpuid
+ shr $24, %ebx
+
+ /* Save the BIST result */
+ cvtsi2sd %ebp, %xmm0
+
+ /* for normal part %ebx already contain cpu_init_detected from fallback call */
+
+ /* Save the cpu_init_detected */
+ cvtsi2sd %ebx, %xmm1
+
+ post_code(0xa1)
+
+ AMD_ENABLE_STACK
+
+ /* Align the stack. */
+ and $0xFFFFFFF0, %esp
+
+#ifdef __x86_64__
+ /* switch to 64 bit long mode */
+ mov %esi, %ecx
+ add $0, %ecx # core number
+ xor %eax, %eax
+ lea (0x1000+0x23)(%ecx), %edi
+ mov %edi, (%ecx)
+ mov %eax, 4(%ecx)
+
+ lea 0x1000(%ecx), %edi
+ movl $0x000000e3, 0x00(%edi)
+ movl %eax, 0x04(%edi)
+ movl $0x400000e3, 0x08(%edi)
+ movl %eax, 0x0c(%edi)
+ movl $0x800000e3, 0x10(%edi)
+ movl %eax, 0x14(%edi)
+ movl $0xc00000e3, 0x18(%edi)
+ movl %eax, 0x1c(%edi)
+
+ # load ROM based identity mapped page tables
+ mov %ecx, %eax
+ mov %eax, %cr3
+
+ # enable PAE
+ mov %cr4, %eax
+ bts $5, %eax
+ mov %eax, %cr4
+
+ # enable long mode
+ mov $0xC0000080, %ecx
+ rdmsr
+ bts $8, %eax
+ wrmsr
+
+ # enable paging
+ mov %cr0, %eax
+ bts $31, %eax
+ mov %eax, %cr0
+
+ # use call far to switch to 64-bit code segment
+ ljmp $0x18, $1f
+1:
+ /* Pass the cpu_init_detected */
+ cvtsd2si %xmm1, %esi
+
+ /* Pass the BIST result */
+ cvtsd2si %xmm0, %edi
+
+#else
+
+ /* Restore the BIST result */
+ cvtsd2si %xmm0, %edx
+
+ /* Restore the cpu_init_detected */
+ cvtsd2si %xmm1, %ebx
+#endif
+
+ /* Must maintain 16-byte stack alignment here. */
+ pushl $0x0
+ pushl $0x0
+ pushl %ebx /* init detected */
+ pushl %edx /* bist */
+
+before_carstage:
+ post_code(0xa2)
+
+ call bootblock_c_entry
+ /* Never reached */
+
+.halt_forever:
+ post_code(POST_DEAD_CODE)
+ hlt
+ jmp .halt_forever
diff --git a/src/soc/amd/common/block/cpu/car/exit_car.S b/src/soc/amd/common/block/cpu/car/exit_car.S
new file mode 100644
index 0000000..46802d9
--- /dev/null
+++ b/src/soc/amd/common/block/cpu/car/exit_car.S
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <gcccar.inc>
+#include <cpu/x86/cache.h>
+
+.code32
+.globl chipset_teardown_car
+
+chipset_teardown_car:
+ /* enable SSE2 128bit instructions */
+ /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
+
+ movl %cr4, %eax
+ orl $(3<<9), %eax
+ movl %eax, %cr4
+
+ /* Save return stack */
+ movd 0(%esp), %xmm1
+ movd %esp, %xmm0
+
+ /* Disable cache */
+ movl %cr0, %eax
+ orl $CR0_CacheDisable, %eax
+ movl %eax, %cr0
+
+ AMD_DISABLE_STACK
+
+ /* enable cache */
+ movl %cr0, %eax
+ andl $0x9fffffff, %eax
+ movl %eax, %cr0
+ xorl %eax, %eax
+
+ /* Restore the return stack */
+ wbinvd
+ movd %xmm0, %esp
+ movd %xmm1, (%esp)
+
+ ret
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 74e0c92..acc4bc0 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -42,6 +42,9 @@
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK
select SOC_AMD_COMMON_BLOCK_PSP
+ select SOC_AMD_COMMON_BLOCK_CAR
+ select C_ENVIRONMENT_BOOTBLOCK
+ select BOOTBLOCK_CONSOLE
config UDELAY_LAPIC_FIXED_FSB
int
@@ -59,6 +62,20 @@
hex
default 0x10000
+config DCACHE_BSP_STACK_SIZE
+ depends on C_ENVIRONMENT_BOOTBLOCK
+ hex
+ default 0x4000
+ help
+ This symbol gets picked up in car.ld when CONFIG_C_ENVIRONMENT_BOOTBLOCK
+ is used. AMD doesn't seem to use this currently.
+
+ todo: Can this and the other 2 DCACHE_RAM_ symbols eventually be
+ condensed?
+
+ The amount of anticipated stack usage in CAR by bootblock and
+ other stages.
+
config CPU_ADDR_BITS
int
default 48
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index bc172f1..031c19b 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -37,6 +37,12 @@
subdirs-y += ../../../cpu/x86/pae
subdirs-y += ../../../cpu/x86/smm
+bootblock-y += early_setup.c
+bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c
+bootblock-y += fixme.c
+bootblock-y += bootblock.c
+
+romstage-y += romstage.c
romstage-y += early_setup.c
romstage-y += dimmSpd.c
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
diff --git a/src/soc/amd/stoneyridge/bootblock.c b/src/soc/amd/stoneyridge/bootblock.c
new file mode 100644
index 0000000..93c181c
--- /dev/null
+++ b/src/soc/amd/stoneyridge/bootblock.c
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation..
+ * Copyright (C) 2017 Advanced Micro Devices
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/early_variables.h>
+#include <console/console.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/bist.h>
+#include <cpu/amd/car.h>
+#include <bootblock_common.h>
+#include <northbridge/amd/pi/agesawrapper.h>
+#include <northbridge/amd/pi/agesawrapper_call.h>
+#include <timestamp.h>
+#include <soc/hudson.h>
+
+asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
+{
+ /* Call lib/bootblock.c main */
+ bootblock_main_with_timestamp(base_timestamp);
+}
+
+void bootblock_soc_early_init(void)
+{
+ amd_initmmio();
+ hudson_lpc_port80();
+ hudson_lpc_decode();
+
+ post_code(0x90);
+ if (CONFIG_STONEYRIDGE_UART)
+ configure_hudson_uart();
+}
+
+void bootblock_soc_init(void)
+{
+ u32 val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ // todo: where to get BIST
+
+ post_code(0x37);
+ AGESAWRAPPER(amdinitreset);
+
+ post_code(0x38);
+ AGESAWRAPPER(amdinitearly);
+}
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h
index 9ecbb13..a9aa1b1 100644
--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h
@@ -23,4 +23,7 @@
void fam15_finalize(void *chip_info);
void setup_uma_memory(void);
+/* todo: remove this when postcar stage is in place */
+asmlinkage void chipset_teardown_car(void);
+
#endif /* NORTHBRIDGE_AMD_AGESA_FAM15H_H */
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
new file mode 100644
index 0000000..b783bd6
--- /dev/null
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/amd/car.h>
+#include <northbridge/amd/pi/agesawrapper.h>
+#include <northbridge/amd/pi/agesawrapper_call.h>
+#include <soc/northbridge.h>
+#include <soc/hudson.h>
+#include <amdblocks/psp.h>
+
+asmlinkage void car_stage_entry(void)
+{
+ console_init();
+
+ if (boot_cpu())
+ amd_initmmio();
+
+ post_code(0x40);
+ AGESAWRAPPER(amdinitpost);
+
+ post_code(0x41);
+ psp_notify_dram();
+
+ post_code(0x42);
+ cbmem_initialize_empty();
+
+ /* This writes contents to DRAM backing before teardown.
+ * todo: move to postcar implementation
+ */
+ chipset_teardown_car();
+
+ post_code(0x43);
+ AGESAWRAPPER(amdinitenv);
+
+ post_code(0x50);
+ copy_and_run();
+
+ post_code(0x54); /* Should never see this post code. */
+}
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index 5c0f08d..1f77ccd 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -145,6 +145,7 @@
@printf " AGESA $(subst $(obj)/,,$(@))\n"
ar rcs $@ $+
+bootblock-libs += $(obj)/agesa/libagesa.a
romstage-libs += $(obj)/agesa/libagesa.a
ramstage-libs += $(obj)/agesa/libagesa.a
--
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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