[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge: Enable early cbmem
Marshall Dawson (Code Review)
gerrit at coreboot.org
Thu May 18 01:43:39 CEST 2017
Marshall Dawson has uploaded a new change for review. ( https://review.coreboot.org/19751 )
Change subject: soc/amd/stoneyridge: Enable early cbmem
......................................................................
soc/amd/stoneyridge: Enable early cbmem
Add a memmap file with a cbmem_top() function. Remove the
LATE_CBMEM_INIT, allowing the default of EARLY. Remove calls
to the late-only set_top_of_ram() function.
Change-Id: I11ad7190031c912642a7312f2fc6f792866288b7
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/stoneyridge/Kconfig
M src/soc/amd/stoneyridge/Makefile.inc
A src/soc/amd/stoneyridge/memmap.c
A src/soc/amd/stoneyridge/memmap.h
M src/soc/amd/stoneyridge/northbridge.c
5 files changed, 111 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/19751/1
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 9c184ed..6584fbb 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -35,7 +35,6 @@
select HAVE_USBDEBUG_OPTIONS
select HAVE_HARD_RESET
select LAPIC_MONOTONIC_TIMER
- select LATE_CBMEM_INIT
select SPI_FLASH if HAVE_ACPI_RESUME
select TSC_SYNC_LFENCE
select SOC_AMD_COMMON
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 3a6ae84..bc172f1 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -45,6 +45,7 @@
romstage-y += smbus.c
romstage-y += smbus_spd.c
romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
+romstage-y += memmap.c
ramstage-y += chip.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
@@ -68,6 +69,7 @@
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
ramstage-y += usb.c
+ramstage-y += memmap.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c
new file mode 100644
index 0000000..8272a40
--- /dev/null
+++ b/src/soc/amd/stoneyridge/memmap.c
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <commonlib/helpers.h>
+#include <cbmem.h>
+#include "memmap.h"
+
+static int installed_gb(void)
+{
+ uint32_t sysmem_mb;
+ msr_t topmem = rdmsr(TOP_MEM);
+ msr_t topmem2 = rdmsr(TOP_MEM2);
+
+ /* Ignore 16MB allocated for C6 when finding UMA size */
+ sysmem_mb = (topmem.lo + (16ull * MiB)) / MiB;
+
+ if (topmem2.hi)
+ sysmem_mb += ((topmem2.hi - 1) * (GiB / MiB * 4)
+ + (topmem2.lo / MiB));
+
+ return sysmem_mb / (GiB / MiB);
+}
+
+/*
+ * Return the size likely assigned to UMA when UMA_AUTO is specified.
+ * This is the only setting the wrapper currently implements. Refer to the
+ * BKDG for Family 15h Model 70h-7Fh Procesors (PID #55072) to find the
+ * following recommended configurations:
+ * Total system memory UMASize
+ * 6G+ 1024M
+ * 4G 512M
+ * 2G 256M
+ */
+size_t uma_size_auto(void)
+{
+ int sysmem_gb = installed_gb();
+
+ if (!IS_ENABLED(CONFIG_GFXUMA))
+ return 0;
+ else if (sysmem_gb >= 6)
+ return 1024 * MiB;
+ else if (sysmem_gb >= 4)
+ return 512 * MiB;
+ else
+ return 256 * MiB;
+}
+
+/*
+ * The BinaryPI image is compiled to always assign UMA below 4GB. It will
+ * also adjust TOM/TOM2 for the C6 storage, as well as the audio controller.
+ */
+uintptr_t uma_base_auto(void)
+{
+ msr_t topmem = rdmsr(TOP_MEM);
+ return topmem.lo - uma_size_auto();
+}
+
+/*
+ * todo: make more flexible if agesawrapper.c changes. The wrapper
+ * currently uses CONFIG_GFXUMA to set UMA_AUTO or UMA_NONE and provides
+ * no opportunity for the mainboard to override it.
+ */
+void *cbmem_top(void)
+{
+ msr_t tom = rdmsr(TOP_MEM);
+
+ if (!tom.lo)
+ return 0;
+ else
+ return (void *)(uma_base_auto() - CONFIG_SMM_TSEG_SIZE);
+}
diff --git a/src/soc/amd/stoneyridge/memmap.h b/src/soc/amd/stoneyridge/memmap.h
new file mode 100644
index 0000000..a57dc31
--- /dev/null
+++ b/src/soc/amd/stoneyridge/memmap.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef NORTHBRIDGE_AMD_MEMMAP_H
+#define NORTHBRIDGE_AMD_MEMMAP_H
+
+uintptr_t uma_base_auto(void);
+size_t uma_size_auto(void);
+
+#endif /* NORTHBRIDGE_AMD_MEMMAP_H */
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 1bc7a35..9c75f0d 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -623,12 +623,8 @@
ramtop = mmio_basek * 1024;
}
- if (IS_ENABLED(CONFIG_GFXUMA)) {
- set_top_of_ram(uma_memory_base);
+ if (IS_ENABLED(CONFIG_GFXUMA))
uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);
- } else {
- set_top_of_ram(ramtop);
- }
for (link = dev->link_list; link; link = link->next) {
if (link->children) {
--
To view, visit https://review.coreboot.org/19751
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: newchange
Gerrit-Change-Id: I11ad7190031c912642a7312f2fc6f792866288b7
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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