[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: configure RAPL PL1 and PL2 for GLK

[Cole Nelson (Code Review)]

Cole Nelson has uploaded a new change for review. ( https://review.coreboot.org/19746 )

Change subject: soc/intel/apollolake: configure RAPL PL1 and PL2 for GLK
......................................................................

soc/intel/apollolake: configure RAPL PL1 and PL2 for GLK

Tested on GLK w/kernel 4.11.0 by reading MSR 0x610 at runtime.

Change-Id: I07caeb2895a579387025d3b0fb7f1d2c3d5e2665
Signed-off-by: Cole Nelson <colex.nelson at intel.com>
---
M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
M src/soc/intel/apollolake/chip.c
M src/soc/intel/common/block/include/intelblocks/msr.h
3 files changed, 11 insertions(+), 4 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/19746/1

diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
index 7809880..127b024 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
@@ -49,10 +49,8 @@
 	# Enable DPTF
 	register "dptf_enable" = "1"
 
-	# PL1 override 12000 mW: the energy calculation is wrong with the
-	# current VR solution. Experiments show that SoC TDP max (6W) can
-	# be reached when RAPL PL1 is set to 12W.
-	register "tdp_pl1_override_mw" = "12000"
+	# PL1 override 
+	register "tdp_pl1_override_mw" = "7500"
 	# Set RAPL PL2 to 15W.
 	register "tdp_pl2_override_mw" = "15000"
 
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 50a285e..1414ea8 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -265,6 +265,13 @@
 	limit.hi = pl2_val & PKG_POWER_LIMIT_MASK;
 	limit.hi |= PKG_POWER_LIMIT_EN;
 
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+       limit.hi |= PKG_POWER_LIMIT_CLAMP;
+       limit.hi |= (MB_POWER_LIMIT2_TIME_DEFAULT &
+               PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT;
+#endif
+
+
 	/* Program package power limits in RAPL MSR */
 	wrmsr(MSR_PKG_POWER_LIMIT, limit);
 	printk(BIOS_INFO, "RAPL PL1 %d.%dW\n", tdp / power_unit,
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index 119c215..8584519 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -74,6 +74,8 @@
  * Y to [21:17] in MSR 0x610. 28 sec is equal to 0x6e.
  */
 #define   MB_POWER_LIMIT1_TIME_DEFAULT	0x6e
+ /* PL2 time window set to approx. 1/10th of PL1 */
+#define MB_POWER_LIMIT2_TIME_DEFAULT	0x4b
 #define MSR_PKG_POWER_SKU		0x614
 #define MSR_DDR_RAPL_LIMIT		0x618
 #define MSR_C_STATE_LATENCY_CONTROL_3	0x633

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I07caeb2895a579387025d3b0fb7f1d2c3d5e2665
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Cole Nelson <colex.nelson at intel.com>