[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Add Intel SATA common code support

Aamir Bohra (Code Review) gerrit at coreboot.org
Wed May 17 20:09:33 CEST 2017


Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/19734 )

Change subject: soc/intel/common: Add Intel SATA common code support
......................................................................


Patch Set 2:

(2 comments)

https://review.coreboot.org/#/c/19734/1/src/soc/intel/common/block/sata/Makefile.inc
File src/soc/intel/common/block/sata/Makefile.inc:

Line 1: ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SATA) += sata.c
> This is not _PCIE
Done.Sorry to miss that.


https://review.coreboot.org/#/c/19734/1/src/soc/intel/common/block/sata/sata.c
File src/soc/intel/common/block/sata/sata.c:

PS1, Line 49: 	port_impl = read32(ahcibar + SATA_ABAR_PORT_IMPLEMENTED) & 0x07;
            : 	/* Port enable */
> This doesn't have the bug fixes from:  https://review.coreboot.org/19553
Ok.Done.Revised under PS#2


-- 
To view, visit https://review.coreboot.org/19734
To unsubscribe, visit https://review.coreboot.org/settings

Gerrit-MessageType: comment
Gerrit-Change-Id: I42ec0059f7e311a232c38fef6a2e050a3e2c0ad3
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Rizwan Qureshi <riz.pro at gmail.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-HasComments: Yes



More information about the coreboot-gerrit mailing list