[coreboot-gerrit] Change in coreboot[master]: [WIP]intel/glkrvp: Add GPE routing settings for GLKRVP.

[Shaunak Saha (Code Review)]

Shaunak Saha has uploaded a new change for review. ( https://review.coreboot.org/19739 )

Change subject: [WIP]intel/glkrvp: Add GPE routing settings for GLKRVP.
......................................................................

[WIP]intel/glkrvp: Add GPE routing settings for GLKRVP.

This patch sets the devicetree for gpe0_dw
configuration and also configures the GPIO lines for SCI.
The macros for LID switch is also set.

Change-Id: I56a99bbb70ac9edda8448fabf05e3ea90d18d93c
Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
---
M src/mainboard/intel/glkrvp/dsdt.asl
M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
M src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h
M src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
4 files changed, 14 insertions(+), 26 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/19739/1

diff --git a/src/mainboard/intel/glkrvp/dsdt.asl b/src/mainboard/intel/glkrvp/dsdt.asl
index 59579c6..f8e9192 100644
--- a/src/mainboard/intel/glkrvp/dsdt.asl
+++ b/src/mainboard/intel/glkrvp/dsdt.asl
@@ -15,7 +15,7 @@
 
 #include <variant/ec.h>
 #define GPE_EC_WAKE	0x26
-#define EC_SCI_GPI	0x25
+#define EC_SCI_GPI	GPE0_DW1_05
 //#include <variant/gpio.h>
 
 DefinitionBlock(
@@ -48,24 +48,6 @@
 	/* Chipset specific sleep states */
 	#include <soc/intel/apollolake/acpi/sleepstates.asl>
 
-#if 0
-	/* LID and Power button. */
-	Scope (\_SB)
-	{
-		Device (LID0)
-		{
-			Name (_HID, EisaId ("PNP0C0D"))
-			Method (_LID, 0)
-			{
-				Return (\_SB.PCI0.LPCB.EC0.LIDS)
-			}
-			Name (_PRW, Package () { GPE_EC_WAKE, 0x3 })
-		}
-		Device (PWRB)
-		{
-			Name (_HID, EisaId ("PNP0C0C"))
-		}
-	}
 	/* Chrome OS Embedded Controller */
 	Scope (\_SB.PCI0.LPCB)
 	{
@@ -85,6 +67,5 @@
 		/* Include common dptf ASL files */
 		#include <soc/intel/common/acpi/dptf/dptf.asl>
 	}
-#endif
 	#include "touchpad.asl"
 }
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
index 7809880..ba88a4c 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
@@ -69,9 +69,12 @@
 	# route, i.e., if this route changes then the affected GPE
 	# offset bits also need to be changed. This sets the PMC register
 	# GPE_CFG fields.
-	register "gpe0_dw1" = "PMC_GPE_N_31_0"
-	register "gpe0_dw2" = "PMC_GPE_N_63_32"
-	register "gpe0_dw3" = "PMC_GPE_SW_31_0"
+	#PMC_GPE_NW_63_32 - 03
+	#PMC_GPE_N_95_64  - 08
+	#PMC_GPE_NW_31_0  - 02
+	register "gpe0_dw1" = "PMC_GPE_NW_63_32"
+	register "gpe0_dw2" = "PMC_GPE_N_95_64"
+	register "gpe0_dw3" = "PMC_GPE_NW_31_0"
 
 	# Enable I2C2 bus early for TPM access
 	register "i2c[2].early_init" = "1"
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h
index f2be328..24bc83d 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h
@@ -61,6 +61,10 @@
 /* Enable EC backed ALS device in ACPI */
 #define EC_ENABLE_ALS_DEVICE
 
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN      GPE_EC_WAKE
+
 /* Enable EC backed PD MCU device in ACPI */
 #define EC_ENABLE_PD_MCU_DEVICE
 
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
index b3aa7e9..16509c2 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
@@ -22,12 +22,12 @@
  * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
  * which is North community
  */
-#define EC_SCI_GPI	0x25	//GPIO_37
+#define EC_SCI_GPI	GPE0_DW1_05//GPIO_37
 
 /* EC SMI */
-#define EC_SMI_GPI	GPIO_49
+#define EC_SMI_GPI	GPIO_41
 
-#define GPE_EC_WAKE	0x26	//GPIO_38
+#define GPE_EC_WAKE	GPE0_DW1_06//GPIO_38
 
 /* Write Protect and indication if EC is in RW code. */
 #define GPIO_PCH_WP	GPIO_75

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I56a99bbb70ac9edda8448fabf05e3ea90d18d93c
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Shaunak Saha <shaunak.saha at intel.com>