[coreboot-gerrit] Change in coreboot[master]: mb/google/eve: Remove FPC device from SPI1

[Duncan Laurie (Code Review)]

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/19728 )

Change subject: mb/google/eve: Remove FPC device from SPI1
......................................................................


mb/google/eve: Remove FPC device from SPI1

This device is no longer directly connected to the SOC so it
does not need to be enabled in coreboot.

BUG=b:35648259
TEST=build and boot on Eve

Change-Id: I4ed5a5575ce51ba5f6f48b54fab42e00134ea351
Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
Reviewed-on: https://review.coreboot.org/19728
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
M src/mainboard/google/eve/devicetree.cb
M src/mainboard/google/eve/gpio.h
2 files changed, 10 insertions(+), 19 deletions(-)

Approvals:
  Aaron Durbin: Looks good to me, approved
  Paul Menzel: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified



diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 97ae3c7..a7388b9 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -207,7 +207,7 @@
 		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
 		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
 		[PchSerialIoIndexSpi0]  = PchSerialIoPci,
-		[PchSerialIoIndexSpi1]  = PchSerialIoPci,
+		[PchSerialIoIndexSpi1]  = PchSerialIoDisabled,
 		[PchSerialIoIndexUart0] = PchSerialIoSkipInit,
 		[PchSerialIoIndexUart1] = PchSerialIoDisabled,
 		[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
@@ -323,16 +323,7 @@
 				device spi 0 on end
 			end
 		end # GSPI #0
-		device pci 1e.3 on
-			chip drivers/spi/acpi
-				register "hid" = "ACPI_DT_NAMESPACE_HID"
-				register "uid" = "1"
-				register "compat_string" = ""fpc,fpc1020""
-				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_HIGH(GPP_C8)"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C9)"
-				device spi 0 on end
-			end
-		end # GSPI #1
+		device pci 1e.3 off end # GSPI #1
 		device pci 1e.4 on  end # eMMC
 		device pci 1e.5 off end # SDIO
 		device pci 1e.6 off end # SDCard
diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h
index ed0d712..b5c2694 100644
--- a/src/mainboard/google/eve/gpio.h
+++ b/src/mainboard/google/eve/gpio.h
@@ -89,10 +89,10 @@
 /* GSPI0_CLK */		PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* DSP */
 /* GSPI0_MISO */	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* DSP */
 /* GSPI0_MOSI */	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* DSP */
-/* GSPI1_CS# */		PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), /* FP */
-/* GSPI1_CLK */		PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), /* FP */
-/* GSPI1_MISO */	PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), /* FP */
-/* GSPI1_MOSI */	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), /* FP */
+/* GSPI1_CS# */		PAD_CFG_NC(GPP_B19),
+/* GSPI1_CLK */		PAD_CFG_NC(GPP_B20),
+/* GSPI1_MISO */	PAD_CFG_NC(GPP_B21),
+/* GSPI1_MOSI */	PAD_CFG_NC(GPP_B22),
 /* SM1ALERT# */		PAD_CFG_NC(GPP_B23),
 
 /* SMBCLK */		PAD_CFG_NC(GPP_C0),
@@ -103,10 +103,10 @@
 /* SML0ALERT# */	PAD_CFG_NC(GPP_C5),
 /* SM1CLK */		PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
 /* SM1DATA */		PAD_CFG_NC(GPP_C7),
-/* UART0_RXD */		PAD_CFG_GPI(GPP_C8, NONE, PLTRST), /* FP_INT */
-/* UART0_TXD */		PAD_CFG_GPI(GPP_C9, NONE, DEEP), /* FP_RST_ODL */
-/* UART0_RTS# */	PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* PCH_FPS_MCU_NRST_ODL */
-/* UART0_CTS# */	PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* PCH_FPS_MCU_BOOT0 */
+/* UART0_RXD */		PAD_CFG_NC(GPP_C8),
+/* UART0_TXD */		PAD_CFG_NC(GPP_C9),
+/* UART0_RTS# */	PAD_CFG_NC(GPP_C10),
+/* UART0_CTS# */	PAD_CFG_NC(GPP_C11),
 /* UART1_RXD */		PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
 /* UART1_TXD */		PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */
 /* UART1_RTS# */	PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */

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Gerrit-MessageType: merged
Gerrit-Change-Id: I4ed5a5575ce51ba5f6f48b54fab42e00134ea351
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>