[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Add Intel PCIe common code

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/19665 )

Change subject: soc/intel/common: Add Intel PCIe common code
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Patch Set 3:

(2 comments)

https://review.coreboot.org/#/c/19665/4/src/soc/intel/common/block/pcie/Kconfig
File src/soc/intel/common/block/pcie/Kconfig:

PS4, Line 11: 	
> Tab then 2 spaces for help text indention
Done.Revised under PS#5


https://review.coreboot.org/#/c/19665/3/src/soc/intel/common/block/pcie/pcie.c
File src/soc/intel/common/block/pcie/pcie.c:

PS3, Line 64: CONFIG_PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE
> But you just hard coded the values. Are these settings applicable to all us
Yes,this would be applied to all SOCs(existing and upcoming 2 generations),verified that the configuration and values is same on upcoming SOCs.


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Gerrit-MessageType: comment
Gerrit-Change-Id: I0c374317a3fe0be0bb1c5d9b16fcbc5cad83ca42
Gerrit-PatchSet: 3
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
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