[coreboot-gerrit] Change in coreboot[master]: amd/gardenia: Switch to soc/amd/stoneyridge
Marc Jones (Code Review)
gerrit at coreboot.org
Wed May 17 00:09:01 CEST 2017
Marc Jones has uploaded a new change for review. ( https://review.coreboot.org/19725 )
Change subject: amd/gardenia: Switch to soc/amd/stoneyridge
......................................................................
amd/gardenia: Switch to soc/amd/stoneyridge
Switch Garnenia mainboard to single soc/ directory structure.
Change-Id: I095804d603bcccf324d3244965081a9dccba62ae
Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
M src/mainboard/amd/gardenia/BiosCallOuts.c
M src/mainboard/amd/gardenia/Kconfig
M src/mainboard/amd/gardenia/Makefile.inc
M src/mainboard/amd/gardenia/devicetree.cb
M src/mainboard/amd/gardenia/dsdt.asl
M src/mainboard/amd/gardenia/fchec.h
M src/mainboard/amd/gardenia/mptable.c
M src/mainboard/amd/gardenia/romstage.c
8 files changed, 59 insertions(+), 70 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/19725/1
diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c
index 23ce0c6..7ff4eb8 100644
--- a/src/mainboard/amd/gardenia/BiosCallOuts.c
+++ b/src/mainboard/amd/gardenia/BiosCallOuts.c
@@ -23,10 +23,10 @@
#include "heapManager.h"
#include "FchPlatform.h"
#include "cbfs.h"
-#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
-#include "imc.h"
+#if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)
+#include <soc/imc.h>
#endif
-#include "hudson.h"
+#include <soc/hudson.h>
#include <stdlib.h>
#include "BiosCallOuts.h"
#include "northbridge/amd/pi/dimmSpd.h"
@@ -95,12 +95,12 @@
} else if (StdHeader->Func == AMD_INIT_ENV) {
FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
-#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
+#if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)
oem_fan_control(FchParams_env);
#endif
/* XHCI configuration */
-#if CONFIG_HUDSON_XHCI_ENABLE
+#if CONFIG_STONEYRIDGE_XHCI_ENABLE
FchParams_env->Usb.Xhci0Enable = TRUE;
#else
FchParams_env->Usb.Xhci0Enable = FALSE;
@@ -109,8 +109,8 @@
FchParams_env->Usb.USB30PortInit = 8; /* 8: If USB3 port is unremoveable. */
/* SATA configuration */
- FchParams_env->Sata.SataClass = CONFIG_HUDSON_SATA_MODE;
- switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) {
+ FchParams_env->Sata.SataClass = CONFIG_STONEYRIDGE_SATA_MODE;
+ switch ((SATA_CLASS)CONFIG_STONEYRIDGE_SATA_MODE) {
case SataRaid:
case SataAhci:
case SataAhci7804:
diff --git a/src/mainboard/amd/gardenia/Kconfig b/src/mainboard/amd/gardenia/Kconfig
index fdf8002..58d952b 100644
--- a/src/mainboard/amd/gardenia/Kconfig
+++ b/src/mainboard/amd/gardenia/Kconfig
@@ -17,15 +17,14 @@
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
- select CPU_AMD_PI_00670F00_FP4
- select NORTHBRIDGE_AMD_PI_00670F00
- select SOUTHBRIDGE_AMD_PI_KERN
+ select SOC_AMD_STONEYRIDGE_FP4
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select GFXUMA
+ select STONEYRIDGE_IMC_FWM
config MAINBOARD_DIR
string
@@ -47,7 +46,7 @@
bool
default y
-config HUDSON_LEGACY_FREE
+config STONEYRIDGE_LEGACY_FREE
bool
default y
diff --git a/src/mainboard/amd/gardenia/Makefile.inc b/src/mainboard/amd/gardenia/Makefile.inc
index 72cd042..ba5e377 100644
--- a/src/mainboard/amd/gardenia/Makefile.inc
+++ b/src/mainboard/amd/gardenia/Makefile.inc
@@ -18,4 +18,4 @@
ramstage-y += BiosCallOuts.c
ramstage-y += OemCustomize.c
-ramstage-$(CONFIG_HUDSON_IMC_FWM) += fchec.c
+ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += fchec.c
diff --git a/src/mainboard/amd/gardenia/devicetree.cb b/src/mainboard/amd/gardenia/devicetree.cb
index be070d0..bb672b2 100644
--- a/src/mainboard/amd/gardenia/devicetree.cb
+++ b/src/mainboard/amd/gardenia/devicetree.cb
@@ -1,7 +1,7 @@
#
# This file is part of the coreboot project.
#
-# Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
+# Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@@ -12,55 +12,45 @@
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
-chip northbridge/amd/pi/00670F00/root_complex
- device cpu_cluster 0 on
- chip cpu/amd/pi/00670F00
- device lapic 10 on end
- end
- end
+chip soc/amd/stoneyridge
+ register "spdAddrLookup" = "
+ {
+ { {0xA2, 0x00} }, // socket 0 - Channel 0, slots 0 & 1
+ }"
+
+ device cpu_cluster 0 on
+ device lapic 10 on end
+ end
device domain 0 on
subsystemid 0x1022 0x1410 inherit
- chip northbridge/amd/pi/00670F00 # CPU side of HT root complex
-
- chip northbridge/amd/pi/00670F00 # PCI side of HT root complex
- device pci 0.0 on end # Root Complex
- device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4
- device pci 1.1 on end # Internal Multimedia
- device pci 2.0 on end # PCIe Host Bridge
- device pci 2.1 on end # x4 PCIe slot
- device pci 2.2 on end # M.2 slot
- device pci 2.3 on end # M.2 slot
- device pci 2.4 on end # x1 PCIe slot
- device pci 2.5 on end # Cardreader
- end #chip northbridge/amd/pi/00670F00
-
- chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus
- device pci 9.0 on end # PCIe Host Bridge
- device pci 9.2 on end # HDA
- device pci 10.0 on end # xHCI
- device pci 11.0 on end # SATA
- device pci 12.0 on end # EHCI
- device pci 14.0 on # SM
- chip drivers/generic/generic # dimm 0-0-0
- device i2c 51 on end
- end
- end # SM
- device pci 14.3 on end # LPC 0x790e
- device pci 14.7 on end # SD
- end #chip southbridge/amd/pi/hudson
-
- device pci 18.0 on end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- device pci 18.4 on end
- device pci 18.5 on end
- register "spdAddrLookup" = "
- {
- { {0xA2, 0x00} }, // socket 0 - Channel 0, slots 0 & 1
- }"
-
- end #chip northbridge/amd/pi/00670F00 # CPU side of HT root complex
+ device pci 0.0 on end # Root Complex
+ device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4
+ device pci 1.1 on end # Internal Multimedia
+ device pci 2.0 on end # PCIe Host Bridge
+ device pci 2.1 on end # x4 PCIe slot
+ device pci 2.2 on end # M.2 slot
+ device pci 2.3 on end # M.2 slot
+ device pci 2.4 on end # x1 PCIe slot
+ device pci 2.5 on end # Cardreader
+ # devices on the NB/SB Link, but on the same pci bus
+ device pci 9.0 on end # PCIe Host Bridge
+ device pci 9.2 on end # HDA
+ device pci 10.0 on end # xHCI
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # EHCI
+ device pci 14.0 on # SM
+ chip drivers/generic/generic # dimm 0-0-0
+ device i2c 51 on end
+ end
+ end # SM
+ device pci 14.3 on end # LPC 0x790e
+ device pci 14.7 on end # SD
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
end #domain
-end #northbridge/amd/pi/00670F00/root_complex
+end #chip soc/amd/stoneyridge
diff --git a/src/mainboard/amd/gardenia/dsdt.asl b/src/mainboard/amd/gardenia/dsdt.asl
index 0d36a60..0ec577d 100644
--- a/src/mainboard/amd/gardenia/dsdt.asl
+++ b/src/mainboard/amd/gardenia/dsdt.asl
@@ -32,13 +32,13 @@
#include "acpi/usb_oc.asl"
/* PCI IRQ mapping for the Southbridge */
- #include <southbridge/amd/pi/hudson/acpi/pcie.asl>
+ #include <soc/amd/stoneyridge/acpi/pcie.asl>
/* Describe the processor tree (\_PR) */
#include <cpu/amd/pi/00670F00/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */
- #include <southbridge/amd/pi/hudson/acpi/sleepstates.asl>
+ #include <soc/amd/stoneyridge/acpi/sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"
@@ -63,11 +63,11 @@
#include <northbridge/amd/pi/00670F00/acpi/northbridge.asl>
/* Describe the AMD Fusion Controller Hub Southbridge */
- #include <southbridge/amd/pi/hudson/acpi/fch.asl>
+ #include <soc/amd/stoneyridge/acpi/fch.asl>
}
/* Describe PCI INT[A-H] for the Southbridge */
- #include <southbridge/amd/pi/hudson/acpi/pci_int.asl>
+ #include <soc/amd/stoneyridge/acpi/pci_int.asl>
/* Describe the devices in the Southbridge */
#include "acpi/carrizo_fch.asl"
@@ -75,7 +75,7 @@
} /* End \_SB scope */
/* Describe SMBUS for the Southbridge */
- #include <southbridge/amd/pi/hudson/acpi/smbus.asl>
+ #include <soc/amd/stoneyridge/acpi/smbus.asl>
/* Define the General Purpose Events for the platform */
#include "acpi/gpe.asl"
diff --git a/src/mainboard/amd/gardenia/fchec.h b/src/mainboard/amd/gardenia/fchec.h
index 7c22063..9fb41b3 100644
--- a/src/mainboard/amd/gardenia/fchec.h
+++ b/src/mainboard/amd/gardenia/fchec.h
@@ -16,7 +16,7 @@
#ifndef AMD_GARDENIA_FCHEC
#define AMD_GARDENIA_FCHEC
-#include "imc.h"
+#include <soc/imc.h>
#include "Porting.h"
#include "AGESA.h"
#include "FchCommonCfg.h"
diff --git a/src/mainboard/amd/gardenia/mptable.c b/src/mainboard/amd/gardenia/mptable.c
index 1c74ae5..5ce380e 100644
--- a/src/mainboard/amd/gardenia/mptable.c
+++ b/src/mainboard/amd/gardenia/mptable.c
@@ -23,7 +23,7 @@
#include <cpu/amd/amdfam15.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
-#include "southbridge/amd/pi/hudson/hudson.h"
+#include <soc/hudson.h>
#include <southbridge/amd/common/amd_pci_util.h>
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c
index 75674a0..1e4e538 100644
--- a/src/mainboard/amd/gardenia/romstage.c
+++ b/src/mainboard/amd/gardenia/romstage.c
@@ -22,7 +22,7 @@
#include <cpu/amd/car.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
+#include <soc/hudson.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
@@ -35,7 +35,7 @@
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
-#if IS_ENABLED(CONFIG_HUDSON_UART)
+#if IS_ENABLED(CONFIG_STONEYRIDGE_UART)
configure_hudson_uart();
#endif
post_code(0x31);
--
To view, visit https://review.coreboot.org/19725
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I095804d603bcccf324d3244965081a9dccba62ae
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Marc Jones <marc at marcjonesconsulting.com>
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