[coreboot-gerrit] Change in coreboot[master]: mainboard/intel/glkrvp: use correct emmc tuning parameters

[Bora Guvendik (Code Review)]

Bora Guvendik has uploaded a new change for review. ( https://review.coreboot.org/19721 )

Change subject: mainboard/intel/glkrvp: use correct emmc tuning parameters
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mainboard/intel/glkrvp: use correct emmc tuning parameters

change the emmc tuning parameters for rvp board

Change-Id: I92e29a313d39de8bd549692a0a1b7817010df5f9
Signed-off-by: Bora Guvendik <bora.guvendik at intel.com>
---
M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
1 file changed, 0 insertions(+), 29 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/19721/1

diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
index 86bb055..7acd636 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
@@ -20,35 +20,6 @@
 	# GPIO for SD card detect
 	register "sdcard_cd_gpio" = "GPIO_186"
 
-	# EMMC TX DATA Delay 1
-	# Refer to EDS-Vol2-22.3.
-	# [14:8] steps of delay for HS400, each 125ps.
-	# [6:0] steps of delay for SDR104/HS200, each 125ps.
-	register "emmc_tx_data_cntl1" = "0x0C16"
-
-	# EMMC TX DATA Delay 2
-	# Refer to EDS-Vol2-22.3.
-	# [30:24] steps of delay for SDR50, each 125ps.
-	# [22:16] steps of delay for DDR50, each 125ps.
-	# [14:8] steps of delay for SDR25/HS50, each 125ps.
-	# [6:0] steps of delay for SDR12, each 125ps.
-	register "emmc_tx_data_cntl2" = "0x28162828"
-
-	# EMMC RX CMD/DATA Delay 1
-	# Refer to EDS-Vol2-22.3.
-	# [30:24] steps of delay for SDR50, each 125ps.
-	# [22:16] steps of delay for DDR50, each 125ps.
-	# [14:8] steps of delay for SDR25/HS50, each 125ps.
-	# [6:0] steps of delay for SDR12, each 125ps.
-	register "emmc_rx_cmd_data_cntl1" = "0x00181717"
-
-	# EMMC RX CMD/DATA Delay 2
-	# Refer to EDS-Vol2-22.3.
-	# [17:16] stands for Rx Clock before Output Buffer
-	# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
-	# [6:0] steps of delay for HS200, each 125ps.
-	register "emmc_rx_cmd_data_cntl2" = "0x10008"
-
 	# Enable DPTF
 	register "dptf_enable" = "1"
 

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Gerrit-MessageType: newchange
Gerrit-Change-Id: I92e29a313d39de8bd549692a0a1b7817010df5f9
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Bora Guvendik <bora.guvendik at intel.com>