[coreboot-gerrit] Change in coreboot[master]: [WIP]src/soc/intel: Patch for SCI/SMI.
Shaunak Saha (Code Review)
gerrit at coreboot.org
Tue May 16 21:03:47 CEST 2017
Shaunak Saha has uploaded a new change for review. ( https://review.coreboot.org/19697 )
Change subject: [WIP]src/soc/intel: Patch for SCI/SMI.
......................................................................
[WIP]src/soc/intel: Patch for SCI/SMI.
This patch adds code for glk SCI/SMI.
Change-Id: I484764ef4f6f815735cfc6615d10d87495d30186
Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
---
M src/mainboard/intel/glkrvp/dsdt.asl
M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
M src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h
M src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
M src/soc/intel/apollolake/gpio_glk.c
M src/soc/intel/apollolake/include/soc/gpio_glk.h
M src/soc/intel/apollolake/include/soc/pm.h
7 files changed, 61 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/19697/4
diff --git a/src/mainboard/intel/glkrvp/dsdt.asl b/src/mainboard/intel/glkrvp/dsdt.asl
index b065019..f7bc34c 100644
--- a/src/mainboard/intel/glkrvp/dsdt.asl
+++ b/src/mainboard/intel/glkrvp/dsdt.asl
@@ -15,7 +15,7 @@
#include <variant/ec.h>
#define GPE_EC_WAKE 0x26
-#define EC_SCI_GPI 0x25
+#define EC_SCI_GPI GPE0_DW1_05
//#include <variant/gpio.h>
DefinitionBlock(
@@ -48,10 +48,10 @@
/* Chipset specific sleep states */
#include <soc/intel/apollolake/acpi/sleepstates.asl>
-#if 0
/* LID and Power button. */
Scope (\_SB)
{
+#if 0
Device (LID0)
{
Name (_HID, EisaId ("PNP0C0D"))
@@ -65,6 +65,7 @@
{
Name (_HID, EisaId ("PNP0C0C"))
}
+#endif
}
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
@@ -85,6 +86,5 @@
/* Include common dptf ASL files */
#include <soc/intel/common/acpi/dptf/dptf.asl>
}
-#endif
#include "touchpad.asl"
}
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
index ed057e0..3fce4f1 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
@@ -72,9 +72,12 @@
# route, i.e., if this route changes then the affected GPE
# offset bits also need to be changed. This sets the PMC register
# GPE_CFG fields.
- register "gpe0_dw1" = "PMC_GPE_N_31_0"
- register "gpe0_dw2" = "PMC_GPE_N_63_32"
- register "gpe0_dw3" = "PMC_GPE_SW_31_0"
+ #PMC_GPE_NW_63_32 - 03
+ #PMC_GPE_N_95_64 - 08
+ #PMC_GPE_NW_31_0 - 02
+ register "gpe0_dw1" = "PMC_GPE_NW_63_32"
+ register "gpe0_dw2" = "PMC_GPE_N_95_64"
+ register "gpe0_dw3" = "PMC_GPE_NW_31_0"
# Enable I2C2 bus early for TPM access
register "i2c[2].early_init" = "1"
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h
index c897a8c..23dd41f 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h
@@ -64,6 +64,10 @@
/* Enable EC backed PD MCU device in ACPI */
#define EC_ENABLE_PD_MCU_DEVICE
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
+
#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
index 24d0d0e..60b204f 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
@@ -22,12 +22,12 @@
* GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
* which is North community
*/
-#define EC_SCI_GPI 0x25 //GPIO_37
+#define EC_SCI_GPI GPE0_DW1_05 //GPIO_37
/* EC SMI */
-#define EC_SMI_GPI GPIO_49
+#define EC_SMI_GPI GPIO_41
-#define GPE_EC_WAKE 0x26 //GPIO_38
+#define GPE_EC_WAKE GPE0_DW1_06 //GPIO_38
/* Write Protect and indication if EC is in RW code. */
#define GPIO_PCH_WP GPIO_75
diff --git a/src/soc/intel/apollolake/gpio_glk.c b/src/soc/intel/apollolake/gpio_glk.c
index 5513e8b..9a2b54c 100644
--- a/src/soc/intel/apollolake/gpio_glk.c
+++ b/src/soc/intel/apollolake/gpio_glk.c
@@ -127,7 +127,18 @@
/* Helper function to map PMC register groups to tier1 sci groups */
int soc_gpe_route_to_gpio(int route)
{
- if ((route >= GPE_NW_31_0) && (route <= GPE_SCC_34_32))
- return route;
- return -1;
+ switch(route) {
+ case PMC_GPE_NW_31_0:
+ return GPIO_GPE_NW_31_0;
+ case PMC_GPE_NW_63_32:
+ return GPIO_GPE_NW_63_32;
+ case PMC_GPE_N_31_0:
+ return GPIO_GPE_N_31_0;
+ case PMC_GPE_N_63_32:
+ return GPIO_GPE_N_63_32;
+ case PMC_GPE_N_95_64:
+ return GPIO_GPE_N_95_64;
+ default:
+ return -1;
+ }
}
diff --git a/src/soc/intel/apollolake/include/soc/gpio_glk.h b/src/soc/intel/apollolake/include/soc/gpio_glk.h
index 35102ca..13c2cc8 100644
--- a/src/soc/intel/apollolake/include/soc/gpio_glk.h
+++ b/src/soc/intel/apollolake/include/soc/gpio_glk.h
@@ -281,15 +281,16 @@
* community. There are 8 GPIO groups: GPP_0 -> GPP_8 (Group 3 is absent)
*/
#define GPIO_MISCCFG 0x10 /* Miscellaneous Configuration offset */
-#define GPE_NW_31_0 0
-#define GPE_NW_63_32 1
-#define GPE_NW_79_64 2
-#define GPE_N_31_0 3
-#define GPE_N_63_32 4
-#define GPE_N_79_64 5
-#define GPE_AUDIO_19_0 6
-#define GPE_SCC_31_0 7
-#define GPE_SCC_34_32 8
+
+#define GPIO_GPE_NW_31_0 0
+#define GPIO_GPE_NW_63_32 1
+#define GPIO_GPE_NW_95_63 2
+#define GPIO_GPE_N_31_0 3
+#define GPIO_GPE_N_63_32 4
+#define GPIO_GPE_N_95_64 5
+#define GPIO_GPE_AUDIO_31_0 6
+#define GPIO_GPE_SCC_31_0 7
+#define GPIO_GPE_SCC_63_32 8
#define GPIO_MAX_NUM_PER_GROUP 32
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index 7db63f6..b2c1b1c 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -165,14 +165,27 @@
#define GPE0_DW2_SHIFT 8
#define GPE0_DW3_SHIFT 12
-#define PMC_GPE_SW_31_0 0
-#define PMC_GPE_SW_63_32 1
-#define PMC_GPE_NW_31_0 3
-#define PMC_GPE_NW_63_32 4
-#define PMC_GPE_NW_95_64 5
-#define PMC_GPE_N_31_0 6
-#define PMC_GPE_N_63_32 7
-#define PMC_GPE_W_31_0 9
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#define PMC_GPE_N_95_64 8 ///< N 64 - 79
+#define PMC_GPE_N_63_32 7 ///< N 34 - 63
+#define PMC_GPE_N_31_0 6 ///< N 0 - 20
+#define PMC_GPE_NW_127_96 5 ///< NW vGPIOs
+#define PMC_GPE_NW_95_64 4 ///< NW 64 - 75, N 76-79
+#define PMC_GPE_NW_63_32 3 ///< NW 32 - 63
+#define PMC_GPE_NW_31_0 2 ///< NW 8 - 31
+#define PMC_GPE_SCC_63_32 1 ///< SCC
+#define PMC_GPE_SCC_31_0 0 ///< SCC
+#else /*For APL*/
+#define PMC_GPE_SW_31_0 0
+#define PMC_GPE_SW_63_32 1
+#define PMC_GPE_NW_31_0 3
+#define PMC_GPE_NW_63_32 4
+#define PMC_GPE_NW_95_64 5
+#define PMC_GPE_N_31_0 6
+#define PMC_GPE_N_63_32 7
+#define PMC_GPE_W_31_0 9
+#endif
+
/* Track power state from reset to log events. */
struct chipset_power_state {
--
To view, visit https://review.coreboot.org/19697
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: newchange
Gerrit-Change-Id: I484764ef4f6f815735cfc6615d10d87495d30186
Gerrit-PatchSet: 4
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Shaunak Saha <shaunak.saha at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi at intel.com>
More information about the coreboot-gerrit
mailing list