[coreboot-gerrit] Change in coreboot[master]: [WIP]soc/intel/skylake: Disable pad tx & rx when in native mode

[Naresh Solanki (Code Review)]

Naresh Solanki has uploaded a new change for review. ( https://review.coreboot.org/19715 )

Change subject: [WIP]soc/intel/skylake: Disable pad tx & rx when in native mode
......................................................................

[WIP]soc/intel/skylake: Disable pad tx & rx when in native mode

When gpio pad is configured in native mode,
Disable gpio pad tx & rx.

TEST=Build for kblrvp & verify native function pins are having
gpio tx & rx disabled.

Change-Id: I074421f5894e19a87cf9a530acd037ce018300e7
Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
---
M src/soc/intel/skylake/include/soc/gpio.h
1 file changed, 3 insertions(+), 2 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/19715/1

diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h
index ae534cd..fdff96d 100644
--- a/src/soc/intel/skylake/include/soc/gpio.h
+++ b/src/soc/intel/skylake/include/soc/gpio.h
@@ -110,13 +110,14 @@
 /* Native Function - No Rx buffer manipulation */
 #define PAD_CFG_NF(pad_, term_, rst_, func_) \
 	_PAD_CFG(pad_, term_, \
-	_DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, func_, NO, NO))
+	_DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, func_, YES \
+	, YES))
 
 /* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S. */
 #define PAD_CFG_NF_1V8(pad_, term_, rst_, func_) \
 	_PAD_CFG_ATTRS(pad_, term_, \
 	_DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, \
-		NO, NO, NO, NO, func_, NO, NO), PAD_FIELD(PAD_TOL, 1V8))
+		NO, NO, NO, NO, func_, YES, YES), PAD_FIELD(PAD_TOL, 1V8))
 
 /* Unused PINS will be controlled by GPIO controller (PMODE = GPIO) and
    GPIO TX/RX will be disabled. */

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I074421f5894e19a87cf9a530acd037ce018300e7
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Naresh Solanki <naresh.solanki at intel.com>