[coreboot-gerrit] Change in coreboot[master]: mainboard/intel/glkrvp: Add support for GLKRVP
Hannah Williams (Code Review)
gerrit at coreboot.org
Mon May 15 17:42:44 CEST 2017
Hannah Williams has uploaded a new change for review. ( https://review.coreboot.org/19604 )
Change subject: mainboard/intel/glkrvp: Add support for GLKRVP
......................................................................
mainboard/intel/glkrvp: Add support for GLKRVP
using SOC_INTEL_GLK
Signed-off-by: Hannah Williams <hannah.williams at intel.com>
Change-Id: Iab688aca6a4f5c5e32801215ba3a1a440e50fbef
---
A src/mainboard/intel/glkrvp/Kconfig
A src/mainboard/intel/glkrvp/Kconfig.name
A src/mainboard/intel/glkrvp/Makefile.inc
A src/mainboard/intel/glkrvp/acpi_tables.c
A src/mainboard/intel/glkrvp/board_info.txt
A src/mainboard/intel/glkrvp/boardid.c
A src/mainboard/intel/glkrvp/bootblock.c
A src/mainboard/intel/glkrvp/chromeos.c
A src/mainboard/intel/glkrvp/chromeos.fmd
A src/mainboard/intel/glkrvp/dsdt.asl
A src/mainboard/intel/glkrvp/ec.c
A src/mainboard/intel/glkrvp/mainboard.c
A src/mainboard/intel/glkrvp/romstage.c
A src/mainboard/intel/glkrvp/smihandler.c
A src/mainboard/intel/glkrvp/touchpad.asl
A src/mainboard/intel/glkrvp/variants/baseboard/Makefile.inc
A src/mainboard/intel/glkrvp/variants/baseboard/boardid.c
A src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
A src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
A src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/acpi/dptf.asl
A src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h
A src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
A src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h
A src/mainboard/intel/glkrvp/variants/baseboard/memory.c
A src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c
A src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/acpi/dptf.asl
A src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/ec.h
A src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/gpio.h
28 files changed, 1,916 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/19604/9
diff --git a/src/mainboard/intel/glkrvp/Kconfig b/src/mainboard/intel/glkrvp/Kconfig
new file mode 100644
index 0000000..96e1669
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/Kconfig
@@ -0,0 +1,90 @@
+
+config BOARD_INTEL_BASEBOARD_GLKRVP
+ def_bool n
+ select SOC_INTEL_GLK
+ select BOARD_ROMSIZE_KB_16384
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_LPC_TPM
+ select MAINBOARD_HAS_TPM2
+# select TPM2
+# select DEBUG_TPM
+
+if BOARD_INTEL_GLKRVP
+
+config BASEBOARD_GLKRVP_LAPTOP
+ def_bool n
+ select SYSTEM_TYPE_LAPTOP
+
+choice
+ prompt "ON BOARD EC"
+ default GLK_CHROME_EC
+ help
+ This option allows you to select the on board EC to use.
+ Select whether the board has Intel EC or Chrome EC
+
+config GLK_CHROME_EC
+ bool "Chrome EC"
+ select EC_GOOGLE_CHROMEEC
+ select EC_GOOGLE_CHROMEEC_LPC
+
+config GLK_INTEL_EC
+ bool "Intel EC"
+ select EC_ACPI
+endchoice
+
+config CHROMEOS
+ bool
+ default y
+ select VIRTUAL_DEV_SWITCH
+ select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
+ select VBOOT_LID_SWITCH
+
+config DRIVERS_I2C_GENERIC
+ default y
+
+config DRIVERS_PS2_KEYBOARD
+ default y
+
+config MAINBOARD_DIR
+ string
+ default intel/glkrvp
+
+config VARIANT_DIR
+ string
+ default "glkrvp" if BOARD_INTEL_GLKRVP
+
+config DEVICETREE
+ string
+ default "variants/baseboard/devicetree.cb"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "glkrvp" if BOARD_INTEL_GLKRVP
+
+config MAINBOARD_FAMILY
+ string
+ default "Intel_Glkrvp" if BOARD_INTEL_GLKRVP
+
+config GBB_HWID
+ string
+ depends on CHROMEOS
+ default "GLKRVP TEST A-A 6939" if BOARD_INTEL_GLKRVP
+
+config MAX_CPUS
+ int
+ default 8
+
+config UART_FOR_CONSOLE
+ int
+ default 2
+
+config INCLUDE_NHLT_BLOBS
+ bool "Include blobs for audio."
+
+config IS_GLK_RVP_1
+ bool "Is this RVP1?"
+ default n
+
+endif # BOARD_INTEL_GLKRVP
diff --git a/src/mainboard/intel/glkrvp/Kconfig.name b/src/mainboard/intel/glkrvp/Kconfig.name
new file mode 100644
index 0000000..b0cfdc5
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/Kconfig.name
@@ -0,0 +1,4 @@
+config BOARD_INTEL_GLKRVP
+ bool "Glkrvp"
+ select BOARD_INTEL_BASEBOARD_GLKRVP
+ select BASEBOARD_GLKRVP_LAPTOP
diff --git a/src/mainboard/intel/glkrvp/Makefile.inc b/src/mainboard/intel/glkrvp/Makefile.inc
new file mode 100644
index 0000000..f2da379
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/Makefile.inc
@@ -0,0 +1,20 @@
+bootblock-y += bootblock.c
+bootblock-y += ec.c
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+romstage-y += boardid.c
+
+ramstage-y += boardid.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-y += ec.c
+ramstage-y += mainboard.c
+
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+subdirs-y += variants/baseboard
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
+
+VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR))
+subdirs-y += variants/$(VARIANT_DIR)
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/intel/glkrvp/acpi_tables.c b/src/mainboard/intel/glkrvp/acpi_tables.c
new file mode 100644
index 0000000..8d4d1cf
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/acpi_tables.c
@@ -0,0 +1,14 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Blank file required by build system assumptions of this file being present.
+ */
diff --git a/src/mainboard/intel/glkrvp/board_info.txt b/src/mainboard/intel/glkrvp/board_info.txt
new file mode 100644
index 0000000..55b5714
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Intel
+Board name: Glkrvp GLK Reference Board
+Category: laptop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/intel/glkrvp/boardid.c b/src/mainboard/intel/glkrvp/boardid.c
new file mode 100644
index 0000000..c5a2e58
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/boardid.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <stddef.h>
+#include <ec/acpi/ec.h>
+
+#define BOARD_ID_GLK_RVP1_DDR4 0x5 /* RVP1 - DDR4 */
+#define BOARD_ID_GLK_RVP2_LP4SD 0x7 /* RVP2 - LP4 Solder Down */
+#define BOARD_ID_GLK_RVP2_LP4 0x8 /* RVP2 - LP4 Socket */
+#define EC_FAB_ID_CMD 0x0D /* Get the board fab ID in the lower 3 bits */
+
+uint8_t board_id(void)
+{
+ MAYBE_STATIC int id = -1;
+ if (id < 0) {
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ id = variant_board_id();
+ else {
+ if(send_ec_command(EC_FAB_ID_CMD) == 0)
+ id = (recv_ec_data() & (0x07));
+ }
+ }
+ return id;
+}
diff --git a/src/mainboard/intel/glkrvp/bootblock.c b/src/mainboard/intel/glkrvp/bootblock.c
new file mode 100644
index 0000000..da66009
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/bootblock.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <bootblock_common.h>
+#include <soc/lpc.h>
+#include <soc/gpio.h>
+#include <variant/ec.h>
+
+void mainboard_ec_init(void);
+
+void bootblock_mainboard_init(void)
+{
+ const struct pad_config *pads;
+ size_t num;
+
+ lpc_configure_pads();
+ pads = variant_early_gpio_table(&num);
+ gpio_configure_pads(pads, num);
+ mainboard_ec_init();
+}
diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c
new file mode 100644
index 0000000..49887ad
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/chromeos.c
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <boot/coreboot_tables.h>
+#include <ec/google/chromeec/ec.h>
+#include <gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <soc/gpio.h>
+#include <variant/gpio.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ struct lb_gpio chromeos_gpios[] = {
+ {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
+ {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
+ {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
+ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+ {-1, ACTIVE_HIGH, 0, "power"},
+ {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+ {GPIO_EC_IN_RW, ACTIVE_HIGH,
+ gpio_get(GPIO_EC_IN_RW), "EC in RW"},
+ };
+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+int get_lid_switch(void)
+{
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ /* Read lid switch state from the EC. */
+ return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN);
+ else
+ return 1;
+}
+
+int get_developer_mode_switch(void)
+{
+ /* No physical developer mode switch. It's virtual. */
+ return 0;
+}
+
+int get_recovery_mode_switch(void)
+{
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ /* Check if the EC has posted the keyboard recovery event. */
+ return !!(google_chromeec_get_events_b() &
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+ return 0;
+}
+
+int clear_recovery_mode_switch(void)
+{
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ /* Clear keyboard recovery event. */
+ return google_chromeec_clear_events_b(
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+ else
+ return 0;
+}
+
+int get_write_protect_state(void)
+{
+ /* Read PCH_WP GPIO. */
+ return gpio_get(GPIO_PCH_WP);
+}
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ const struct cros_gpio *gpios;
+ size_t num;
+
+ gpios = variant_cros_gpios(&num);
+ chromeos_acpi_gpio_generate(gpios, num);
+}
diff --git a/src/mainboard/intel/glkrvp/chromeos.fmd b/src/mainboard/intel/glkrvp/chromeos.fmd
new file mode 100644
index 0000000..116d025
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/chromeos.fmd
@@ -0,0 +1,54 @@
+FLASH 16M {
+ WP_RO at 0x0 0x400000 {
+ SI_DESC at 0x0 0x1000
+ IFWI at 0x1000 0x1ff000
+ RO_VPD at 0x200000 0x4000
+ RO_SECTION at 0x204000 0x1fc000 {
+ FMAP at 0x0 0x800
+ RO_FRID at 0x800 0x40
+ RO_FRID_PAD at 0x840 0x7c0
+ COREBOOT(CBFS)@0x1000 0x19b000
+ GBB at 0x19c000 0x40000
+ RO_UNUSED at 0x1dc000 0x20000
+ }
+ }
+ MISC_RW at 0x400000 0x4a000 {
+ UNIFIED_MRC_CACHE at 0x0 0x21000 {
+ RECOVERY_MRC_CACHE at 0x0 0x10000
+ RW_MRC_CACHE at 0x10000 0x10000
+ RW_VAR_MRC_CACHE at 0x20000 0x1000
+ }
+ RW_ELOG at 0x21000 0x4000
+ RW_SHARED at 0x25000 0x4000 {
+ SHARED_DATA at 0x0 0x2000
+ VBLOCK_DEV at 0x2000 0x2000
+ }
+ RW_VPD at 0x29000 0x2000
+ TMP_UNUSED_HOLE at 0x2B000 0x1F000
+ }
+ RW_SECTION_A at 0x44a000 0x477800 {
+ VBLOCK_A at 0x0 0x10000
+ FW_MAIN_A(CBFS)@0x10000 0x4677c0
+ RW_FWID_A at 0x4777c0 0x40
+ }
+ RW_SECTION_B at 0x8c1800 0x477800 {
+ VBLOCK_B at 0x0 0x10000
+ FW_MAIN_B(CBFS)@0x10000 0x4677c0
+ RW_FWID_B at 0x4777c0 0x40
+ }
+ RW_NVRAM at 0xd39000 0x6000
+ RW_LEGACY(CBFS)@0xd3f000 0x200000
+ BIOS_UNUSABLE at 0xf3f000 0x40000
+ DEVICE_EXTENSION at 0xf7f000 0x80000
+ # Currently, it is required that the BIOS region be a multiple of 8KiB.
+ # This is required so that the recovery mechanism can find SIGN_CSE
+ # region aligned to 4K at the center of BIOS region. Since the
+ # descriptor at the beginning uses 4K and BIOS starts at an offset of
+ # 4K, a hole of 4K is created towards the end of the flash to compensate
+ # for the size requirement of BIOS region.
+ # FIT tool thus creates descriptor with following regions:
+ # Descriptor --> 0 to 4K
+ # BIOS --> 4K to 0xf7f000
+ # Device ext --> 0xf7f000 to 0xfff000
+ UNUSED_HOLE at 0xfff000 0x1000
+}
diff --git a/src/mainboard/intel/glkrvp/dsdt.asl b/src/mainboard/intel/glkrvp/dsdt.asl
new file mode 100644
index 0000000..59579c6
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/dsdt.asl
@@ -0,0 +1,90 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <variant/ec.h>
+#define GPE_EC_WAKE 0x26
+#define EC_SCI_GPI 0x25
+//#include <variant/gpio.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x05, // DSDT revision: ACPI v5.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ /* global NVS and variables */
+ #include <soc/intel/apollolake/acpi/globalnvs.asl>
+
+ /* CPU */
+ #include <soc/intel/apollolake/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/apollolake/acpi/northbridge.asl>
+ #include <soc/intel/apollolake/acpi/southbridge.asl>
+ #include <soc/intel/apollolake/acpi/pch_hda.asl>
+ }
+ }
+
+ /* Chrome OS specific */
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+ /* Chipset specific sleep states */
+ #include <soc/intel/apollolake/acpi/sleepstates.asl>
+
+#if 0
+ /* LID and Power button. */
+ Scope (\_SB)
+ {
+ Device (LID0)
+ {
+ Name (_HID, EisaId ("PNP0C0D"))
+ Method (_LID, 0)
+ {
+ Return (\_SB.PCI0.LPCB.EC0.LIDS)
+ }
+ Name (_PRW, Package () { GPE_EC_WAKE, 0x3 })
+ }
+ Device (PWRB)
+ {
+ Name (_HID, EisaId ("PNP0C0C"))
+ }
+ }
+ /* Chrome OS Embedded Controller */
+ Scope (\_SB.PCI0.LPCB)
+ {
+ /* ACPI code for EC SuperIO functions */
+ #include <ec/google/chromeec/acpi/superio.asl>
+ /* ACPI code for EC functions */
+ #include <ec/google/chromeec/acpi/ec.asl>
+ }
+
+ /* Dynamic Platform Thermal Framework */
+ Scope (\_SB)
+ {
+ /* Per board variant specific definitions. */
+ #include <variant/acpi/dptf.asl>
+ /* Include soc specific DPTF changes */
+ #include <soc/intel/apollolake/acpi/dptf.asl>
+ /* Include common dptf ASL files */
+ #include <soc/intel/common/acpi/dptf/dptf.asl>
+ }
+#endif
+ #include "touchpad.asl"
+}
diff --git a/src/mainboard/intel/glkrvp/ec.c b/src/mainboard/intel/glkrvp/ec.c
new file mode 100644
index 0000000..edbd45a
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/ec.c
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include <rules.h>
+#include <soc/lpc.h>
+#include <variant/ec.h>
+
+void mainboard_ec_init(void);
+
+static void ramstage_ec_init(void)
+{
+ printk(BIOS_ERR, "mainboard: EC init\n");
+
+ if (acpi_is_wakeup_s3()) {
+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+ MAINBOARD_EC_S3_WAKE_EVENTS);
+
+ /* Disable SMI and wake events */
+ google_chromeec_set_smi_mask(0);
+
+ /* Clear pending events */
+ while (google_chromeec_get_event() != 0)
+ ;
+
+ /* Restore SCI event mask */
+ google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
+ } else {
+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+ MAINBOARD_EC_S5_WAKE_EVENTS);
+ }
+
+ /* Clear wake event mask */
+ google_chromeec_set_wake_mask(0);
+}
+
+static void bootblock_ec_init(void)
+{
+ uint16_t ec_ioport_base;
+ size_t ec_ioport_size;
+ /*
+ * Set up LPC decoding for the ChromeEC I/O port ranges:
+ * - Ports 62/66, 60/64, and 200->208
+ * - ChromeEC specific communication I/O ports.
+ */
+ lpc_enable_fixed_io_ranges(IOE_EC_62_66 | IOE_KBC_60_64 | IOE_LGE_200);
+ google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size);
+ lpc_open_pmio_window(ec_ioport_base, ec_ioport_size);
+}
+
+void mainboard_ec_init(void)
+{
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ {
+ if (ENV_RAMSTAGE)
+ ramstage_ec_init();
+ else if (ENV_BOOTBLOCK)
+ bootblock_ec_init();
+ }
+ else {
+ if (ENV_BOOTBLOCK)
+ lpc_enable_fixed_io_ranges(IOE_EC_62_66 | IOE_KBC_60_64 | IOE_LGE_200);
+ }
+
+ if (IS_ENABLED(CONFIG_GLK_INTEL_EC))
+ {
+ printk(BIOS_ERR, "S3 Hack Enable ACPI mode: outb(0xaa, 0x66)\n");
+ outb(0xaa, 0x66);
+ }
+}
diff --git a/src/mainboard/intel/glkrvp/mainboard.c b/src/mainboard/intel/glkrvp/mainboard.c
new file mode 100644
index 0000000..016c9ac
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/mainboard.c
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <nhlt.h>
+#include <soc/gpio.h>
+#include <soc/nhlt.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <variant/ec.h>
+#include <variant/gpio.h>
+
+void mainboard_ec_init(void);
+
+static void mainboard_init(void *chip_info)
+{
+ int boardid;
+ const struct pad_config *pads;
+ size_t num;
+
+ boardid = board_id();
+ printk(BIOS_INFO, "Board ID: %d\n", boardid);
+
+ pads = variant_gpio_table(&num);
+ gpio_configure_pads(pads, num);
+
+ mainboard_ec_init();
+}
+
+static unsigned long mainboard_write_acpi_tables(
+ device_t device, unsigned long current, acpi_rsdp_t *rsdp)
+{
+ uintptr_t start_addr;
+ uintptr_t end_addr;
+ struct nhlt *nhlt;
+
+ start_addr = current;
+
+ nhlt = nhlt_init();
+
+ if (nhlt == NULL)
+ return start_addr;
+
+ variant_nhlt_init(nhlt);
+
+ end_addr = nhlt_soc_serialize(nhlt, start_addr);
+
+ if (end_addr != start_addr)
+ acpi_add_table(rsdp, (void *)start_addr);
+
+ return end_addr;
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
+}
+
+struct chip_operations mainboard_ops = {
+ .init = mainboard_init,
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/intel/glkrvp/romstage.c b/src/mainboard/intel/glkrvp/romstage.c
new file mode 100644
index 0000000..9d5be63
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/romstage.c
@@ -0,0 +1,243 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <string.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+#define BOARD_ID_GLK_RVP1_DDR4 0x5 /* GLK RVP1 - DDR4 */
+#define BOARD_ID_GLK_RVP2_LP4SD 0x7 /* GLK RVP2 - LP4 Solder Down */
+#define BOARD_ID_GLK_RVP2_LP4 0x8 /* RVP2 - LP4 Socket */
+
+/* DDR4 specific swizzling data start */
+
+/* Channel 0 PHY 0 to DUnit DQ mapping */
+static const uint8_t swizzling_ch0_ddr4[] = {
+ 15, 14, 10, 11, 8, 9, 13, 12, 2, 7, 3, 6, 4, 0, 1, 5,
+ 29, 31, 27, 26, 24, 28, 25, 30, 19, 22, 18, 21, 23, 16, 17, 20,
+};
+
+/* Channel 1 PHY 0 to DUnit DQ mapping */
+static const uint8_t swizzling_ch1_ddr4[] = {
+ 1, 0, 4, 5, 7, 2, 6, 3, 24, 25, 28, 30, 26, 27, 31, 29,
+ 21, 20, 17, 16, 23, 22, 19, 18, 8, 12, 11, 15, 10, 9, 13, 14,
+};
+
+/* Channel 1 PHY 1 to DUnit DQ mapping */
+static const uint8_t swizzling_ch2_ddr4[] = {
+ 14, 12, 9, 13, 10, 15, 11, 8, 1, 3, 7, 5, 2, 6, 0, 4,
+ 27, 24, 29, 28, 30, 26, 31, 25, 19, 20, 18, 22, 16, 21, 23, 17,
+};
+
+/* Channel 0 PHY 1 to DUnit DQ mapping */
+static const uint8_t swizzling_ch3_ddr4[] = {
+ 12, 8, 13, 9, 15, 11, 14, 10, 0, 5, 1, 4, 7, 2, 6, 3,
+ 20, 16, 21, 17, 19, 18, 22, 23, 29, 24, 28, 26, 25, 30, 31, 27
+};
+/* DDR4 specific swizzling data end*/
+
+/* LPDD4 specific swizzling data start */
+
+/* Channel 0 PHY 0 to DUnit DQ mapping */
+static const uint8_t swizzling_ch0_lpddr4[] = {
+ 10, 8, 12, 11, 9, 13, 14, 15, 1, 3, 2, 0, 5, 4, 6, 7,
+ 30, 26, 24, 25, 28, 29, 31, 27, 20, 21, 22, 16, 23, 17, 18, 19,
+};
+
+/* Channel 1 PHY 0 to DUnit DQ mapping */
+static const uint8_t swizzling_ch1_lpddr4[] = {
+ 0, 6, 7, 5, 3, 2, 1, 4, 12, 15, 13, 8, 9, 10, 11, 14,
+ 17, 18, 19, 16, 23, 20, 21, 22, 30, 31, 25, 27, 26, 29, 28, 24,
+};
+
+/* Channel 1 PHY 1 to DUnit DQ mapping */
+static const uint8_t swizzling_ch2_lpddr4[] = {
+ 15, 8, 11, 10, 14, 12, 13, 9, 5, 1, 0, 6, 2, 3, 7, 4,
+ 31, 25, 24, 27, 30, 29, 28, 26, 21, 18, 20, 23, 16, 17, 22, 19,
+};
+
+/* Channel 0 PHY 1 to DUnit DQ mapping */
+static const uint8_t swizzling_ch3_lpddr4[] = {
+ 15, 9, 8, 10, 13, 14, 12, 11, 7, 6, 5, 0, 4, 2, 1, 3,
+ 20, 21, 23, 22, 19, 17, 18, 16, 24, 27, 26, 30, 25, 31, 28, 29
+};
+/* LPDD4 specific swizzling data end */
+
+static void fill_lpddr4_params(FSP_M_CONFIG *cfg)
+{
+ cfg->Package = 1;
+ cfg->MemoryDown = 1;
+ cfg->DDR3LPageSize = 0;
+ cfg->DDR3LASR = 0;
+ cfg->ScramblerSupport = 1;
+ cfg->ChannelHashMask = 0x36;
+ cfg->SliceHashMask = 0x9;
+ cfg->InterleavedMode = 2;
+ cfg->ChannelsSlicesEnable = 0;
+ cfg->MinRefRate2xEnable = 0;
+ cfg->DualRankSupportEnable = 0;
+ cfg->DisableFastBoot = 0;
+ cfg->RmtMode = 0;
+ cfg->RmtCheckRun = 0;
+ cfg->RmtMarginCheckScaleHighThreshold = 0;
+ cfg->MemorySizeLimit = 0;
+ cfg->LowMemoryMaxValue = 0;
+ cfg->HighMemoryMaxValue = 0;
+ cfg->Profile = 7;
+ cfg->DIMM0SPDAddress = 0x00;
+ cfg->DIMM1SPDAddress = 0x00;
+ cfg->Ch0_RankEnable = 0x1;
+ cfg->Ch0_DeviceWidth = 0x1;
+ cfg->Ch0_DramDensity = 0x2;
+ cfg->Ch0_Option = 0x3;
+ cfg->Ch0_TristateClk1 = 0;
+ cfg->Ch0_Mode2N = 0;
+ cfg->Ch0_OdtLevels = 0;
+ cfg->Ch1_RankEnable = 0x1;
+ cfg->Ch1_DeviceWidth = 0x1;
+ cfg->Ch1_DramDensity = 0x2;
+ cfg->Ch1_Option = 0x3;
+ cfg->Ch1_TristateClk1 = 0;
+ cfg->Ch1_Mode2N = 0;
+ cfg->Ch1_OdtLevels = 0;
+ cfg->Ch2_RankEnable = 0x1;
+ cfg->Ch2_DeviceWidth = 0x1;
+ cfg->Ch2_DramDensity = 0x2;
+ cfg->Ch2_Option = 0x3;
+ cfg->Ch2_TristateClk1 = 0;
+ cfg->Ch2_Mode2N = 0;
+ cfg->Ch2_OdtLevels = 0;
+ cfg->Ch3_RankEnable = 0x1;
+ cfg->Ch3_DeviceWidth = 0x1;
+ cfg->Ch3_DramDensity = 0x2;
+ cfg->Ch3_Option = 0x3;
+ cfg->Ch3_TristateClk1 = 0;
+ cfg->Ch3_Mode2N = 0;
+ cfg->Ch3_OdtLevels = 0;
+ /* phy0 ch0 */
+ memcpy(cfg->Ch0_Bit_swizzling, swizzling_ch0_lpddr4,
+ sizeof(swizzling_ch0_lpddr4));
+ /* phy0 ch1 */
+ memcpy(cfg->Ch1_Bit_swizzling, swizzling_ch1_lpddr4,
+ sizeof(swizzling_ch1_lpddr4));
+ /* phy1 ch1 */
+ memcpy(cfg->Ch2_Bit_swizzling, swizzling_ch2_lpddr4,
+ sizeof(swizzling_ch2_lpddr4));
+ /* phy1 ch0 */
+ memcpy(cfg->Ch3_Bit_swizzling, swizzling_ch3_lpddr4,
+ sizeof(swizzling_ch3_lpddr4));
+}
+
+static void fill_ddr4_params(FSP_M_CONFIG *cfg)
+{
+ cfg->Package = 0; /* 0x1:BGA */
+ cfg->MemoryDown = 0;
+ cfg->DDR3LPageSize = 1;
+ cfg->DDR3LASR = 0;
+ cfg->ScramblerSupport = 0;
+ cfg->ChannelHashMask = 0x36;
+ cfg->SliceHashMask = 0x9;
+ cfg->InterleavedMode = 0;
+ cfg->ChannelsSlicesEnable = 0;
+ cfg->MinRefRate2xEnable = 0;
+ cfg->DualRankSupportEnable = 1;
+ cfg->DisableFastBoot = 0;
+ cfg->RmtMode = 0;
+ cfg->RmtCheckRun = 0;
+ cfg->RmtMarginCheckScaleHighThreshold = 0;
+ cfg->MemorySizeLimit = 0;
+ cfg->LowMemoryMaxValue = 0;
+ cfg->HighMemoryMaxValue = 0;
+ cfg->Profile = 11;
+ cfg->DIMM0SPDAddress = 0xA0;
+ cfg->DIMM1SPDAddress = 0xA4;
+ cfg->Ch0_RankEnable = 0x3;
+ cfg->Ch0_DeviceWidth = 0x1;
+ cfg->Ch0_DramDensity = 0x0;
+ cfg->Ch0_Option = 0x3; /* Bank Address Hashing enabled */
+ cfg->Ch0_TristateClk1 = 0;
+ cfg->Ch0_Mode2N = 0;
+ cfg->Ch0_OdtLevels = 0;
+ cfg->Ch1_RankEnable = 0x3;
+ cfg->Ch1_DeviceWidth = 0x1;
+ cfg->Ch1_DramDensity = 0x2;
+ cfg->Ch1_Option = 0x3; /* Bank Address Hashing enabled */
+ cfg->Ch1_TristateClk1 = 0;
+ cfg->Ch1_Mode2N = 0;
+ cfg->Ch1_OdtLevels = 0;
+ cfg->Ch2_RankEnable = 0x0;
+ cfg->Ch2_DeviceWidth = 0x1;
+ cfg->Ch2_DramDensity = 0x2;
+ cfg->Ch2_Option = 0x3; /* Bank Address Hashing enabled */
+ cfg->Ch2_TristateClk1 = 0;
+ cfg->Ch2_Mode2N = 0;
+ cfg->Ch2_OdtLevels = 0;
+ cfg->Ch3_RankEnable = 0x0;
+ cfg->Ch3_DeviceWidth = 0x1;
+ cfg->Ch3_DramDensity = 0x2;
+ cfg->Ch3_Option = 0x3; /* Bank Address Hashing enabled */
+ cfg->Ch3_TristateClk1 = 0;
+ cfg->Ch3_Mode2N = 0;
+ cfg->Ch3_OdtLevels = 0;
+
+ /* phy0 ch0 */
+ memcpy(cfg->Ch0_Bit_swizzling, swizzling_ch0_ddr4,
+ sizeof(swizzling_ch0_ddr4));
+ /* phy0 ch1 */
+ memcpy(cfg->Ch1_Bit_swizzling, swizzling_ch1_ddr4,
+ sizeof(swizzling_ch1_ddr4));
+ /* phy1 ch1 */
+ memcpy(cfg->Ch2_Bit_swizzling, swizzling_ch2_ddr4,
+ sizeof(swizzling_ch2_ddr4));
+ /* phy1 ch0 */
+ memcpy(cfg->Ch3_Bit_swizzling, swizzling_ch3_ddr4,
+ sizeof(swizzling_ch3_ddr4));
+}
+
+static void fill_memory_params(FSP_M_CONFIG *cfg)
+{
+ uint8_t boardid;
+
+ if (IS_ENABLED(CONFIG_IS_GLK_RVP_1))
+ boardid = BOARD_ID_GLK_RVP1_DDR4;
+ else
+ boardid = BOARD_ID_GLK_RVP2_LP4;
+
+ switch (boardid) {
+ case BOARD_ID_GLK_RVP1_DDR4:
+ fill_ddr4_params(cfg);
+ break;
+ case BOARD_ID_GLK_RVP2_LP4SD:
+ case BOARD_ID_GLK_RVP2_LP4:
+ fill_lpddr4_params(cfg);
+ break;
+ }
+}
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+ FSP_M_CONFIG *cfg = &memupd->FspmConfig;
+ fill_memory_params(cfg);
+#if 0
+ meminit_lpddr4_by_sku(&memupd->FspmConfig,
+ variant_lpddr4_config(), variant_memory_sku());
+#endif
+}
+
+void mainboard_save_dimm_info(void)
+{
+ save_lpddr4_dimm_info(variant_lpddr4_config(), variant_memory_sku());
+}
diff --git a/src/mainboard/intel/glkrvp/smihandler.c b/src/mainboard/intel/glkrvp/smihandler.c
new file mode 100644
index 0000000..5a59d46
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/smihandler.c
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <baseboard/variants.h>
+#include <cpu/x86/smm.h>
+#include <ec/google/chromeec/smm.h>
+#include <soc/pm.h>
+#include <soc/smm.h>
+#include <soc/gpio.h>
+#include <variant/ec.h>
+#include <variant/gpio.h>
+
+void mainboard_smi_gpi_handler(const struct gpi_status *sts)
+{
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (gpi_status_get(sts, EC_SMI_GPI))
+ chromeec_smi_process_events();
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ const struct pad_config *pads;
+ size_t num;
+
+ pads = variant_sleep_gpio_table(&num);
+ gpio_configure_pads(pads, num);
+
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
+ MAINBOARD_EC_S5_WAKE_EVENTS);
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
+ MAINBOARD_EC_SMI_EVENTS);
+ return 0;
+}
diff --git a/src/mainboard/intel/glkrvp/touchpad.asl b/src/mainboard/intel/glkrvp/touchpad.asl
new file mode 100644
index 0000000..73ed720
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/touchpad.asl
@@ -0,0 +1,63 @@
+#define GPIO_18_IRQ 0x3C
+ Scope (\_SB.PCI0.I2C4)
+ {
+ Device (TPAD)
+ {
+ Name(_ADR, One)
+ Name (_HID, "ALPS0001")
+ Name (_CID, "PNP0C50")
+ Name (_DDN, "ALPS Touchpad")
+ Name (_UID, 1)
+ Name (ISTP, 1) /* Touchpad */
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x2C, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.PCI0.I2C4", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Level, ActiveLow)
+ {
+ GPIO_18_IRQ
+ }
+ GpioInt (Level, ActiveLow, ExclusiveAndWake, PullUp, 0x0000, "\\_SB.GPO1", 0x00, ResourceConsumer, ,)
+ {
+ 18
+ }
+ })
+
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+ Method(_DSM, 0x4, NotSerialized)
+ {
+ // DSM UUID for HIDI2C - HID driver does not load without DSM
+ If(LEqual(Arg0, ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE")))
+ {
+ // Function 0 : Query Function
+ If(LEqual(Arg2, Zero))
+ {
+ // Revision 1
+ If(LEqual(Arg1, One))
+ {
+ Return (Buffer (One) {0x03})
+ }
+ Else
+ {
+ Return (Buffer (One) {0x00})
+ }
+ } ElseIf (LEqual(Arg2, One)) { // Function 1 : HID Function
+ // HID Descriptor Address (IHV Specific)
+ Return(0x0020)
+ } Else {
+ Return (Buffer (One) {0x00})
+ }
+ } Else {
+ Return (Buffer (One) {0x00})
+ }
+ }
+ }
+}
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/Makefile.inc b/src/mainboard/intel/glkrvp/variants/baseboard/Makefile.inc
new file mode 100644
index 0000000..d2d344c
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/Makefile.inc
@@ -0,0 +1,10 @@
+bootblock-y += gpio.c
+
+romstage-y += boardid.c
+romstage-y += memory.c
+
+ramstage-y += boardid.c
+ramstage-y += gpio.c
+ramstage-y += nhlt.c
+
+smm-y += gpio.c
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c
new file mode 100644
index 0000000..51641e3
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <ec/google/chromeec/ec.h>
+
+uint8_t __attribute__((weak)) variant_board_id(void)
+{
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ return google_chromeec_get_board_version();
+ else
+ return 0;
+}
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
new file mode 100644
index 0000000..7809880
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
@@ -0,0 +1,139 @@
+chip soc/intel/apollolake
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ register "pcie_rp0_clkreq_pin" = "CLKREQ_DISABLED"
+ # Disable unused clkreq of PCIe root ports
+ register "pcie_rp1_clkreq_pin" = "3" # wifi/bt
+ register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp4_clkreq_pin" = "1"
+ register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+
+ # GPIO for PERST_0
+ # If the Board has PERST_0 signal, assign the GPIO
+ # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
+ register "prt0_gpio" = "GPIO_PRT0_UDEF"
+
+ # EMMC TX DATA Delay 1
+ # Refer to EDS-Vol2-22.3.
+ # [14:8] steps of delay for HS400, each 125ps.
+ # [6:0] steps of delay for SDR104/HS200, each 125ps.
+ register "emmc_tx_data_cntl1" = "0x0C16"
+
+ # EMMC TX DATA Delay 2
+ # Refer to EDS-Vol2-22.3.
+ # [30:24] steps of delay for SDR50, each 125ps.
+ # [22:16] steps of delay for DDR50, each 125ps.
+ # [14:8] steps of delay for SDR25/HS50, each 125ps.
+ # [6:0] steps of delay for SDR12, each 125ps.
+ register "emmc_tx_data_cntl2" = "0x28162828"
+
+ # EMMC RX CMD/DATA Delay 1
+ # Refer to EDS-Vol2-22.3.
+ # [30:24] steps of delay for SDR50, each 125ps.
+ # [22:16] steps of delay for DDR50, each 125ps.
+ # [14:8] steps of delay for SDR25/HS50, each 125ps.
+ # [6:0] steps of delay for SDR12, each 125ps.
+ register "emmc_rx_cmd_data_cntl1" = "0x00181717"
+
+ # EMMC RX CMD/DATA Delay 2
+ # Refer to EDS-Vol2-22.3.
+ # [17:16] stands for Rx Clock before Output Buffer
+ # [14:8] steps of delay for Auto Tuning Mode, each 125ps.
+ # [6:0] steps of delay for HS200, each 125ps.
+ register "emmc_rx_cmd_data_cntl2" = "0x10008"
+
+ # Enable DPTF
+ register "dptf_enable" = "1"
+
+ # PL1 override 12000 mW: the energy calculation is wrong with the
+ # current VR solution. Experiments show that SoC TDP max (6W) can
+ # be reached when RAPL PL1 is set to 12W.
+ register "tdp_pl1_override_mw" = "12000"
+ # Set RAPL PL2 to 15W.
+ register "tdp_pl2_override_mw" = "15000"
+
+ # Enable Audio Clock and Power gating
+ register "hdaudio_clk_gate_enable" = "1"
+ register "hdaudio_pwr_gate_enable" = "1"
+ register "hdaudio_bios_config_lockdown" = "1"
+
+ # Enable lpss s0ix
+ register "lpss_s0ix_enable" = "1"
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route, i.e., if this route changes then the affected GPE
+ # offset bits also need to be changed. This sets the PMC register
+ # GPE_CFG fields.
+ register "gpe0_dw1" = "PMC_GPE_N_31_0"
+ register "gpe0_dw2" = "PMC_GPE_N_63_32"
+ register "gpe0_dw3" = "PMC_GPE_SW_31_0"
+
+ # Enable I2C2 bus early for TPM access
+ register "i2c[2].early_init" = "1"
+
+ # Minimum SLP S3 assertion width 28ms.
+ register "slp_s3_assertion_width_usecs" = "28000"
+
+ device domain 0 on
+ device pci 00.0 on end # - Host Bridge
+ device pci 00.1 on end # - DPTF
+ device pci 00.2 on end # - NPK
+ device pci 02.0 on end # - Gen
+ device pci 03.0 on end # - Iunit
+ device pci 0c.0 on end # - CNVi
+ device pci 0d.0 on end # - P2SB
+ device pci 0d.1 on end # - PMC
+ device pci 0d.2 on end # - SPI
+ device pci 0d.3 on end # - Shared SRAM
+ device pci 0e.0 on end # - Audio
+ device pci 0f.0 on end # - Heci1
+ device pci 0f.1 on end # - Heci2
+ device pci 0f.2 on end # - Heci3
+ device pci 11.0 off end # - ISH
+ device pci 12.0 on end # - SATA
+ device pci 13.0 off end # - PCIe-A 0 Slot 1
+ device pci 13.1 off end # - PCIe-A 1
+ device pci 13.2 on end # - PCIe-A 2 Onboard Lan
+ device pci 13.3 off end # - PCIe-A 3
+ device pci 14.0 off end # - PCIe-B 0 Slot2
+ device pci 14.1 on end # - PCIe-B 1 Onboard M2 Slot(Wifi/BT)
+ device pci 15.0 on end # - XHCI
+ device pci 15.1 off end # - XDCI
+ device pci 16.0 on end # - I2C 0
+ device pci 16.1 off end # - I2C 1
+ device pci 16.2 off end # - I2C 2
+ device pci 16.3 off end # - I2C 3
+ device pci 17.0 on end # - I2C 4
+ device pci 17.1 off end # - I2C 5
+ device pci 17.2 off end # - I2C 6
+ device pci 17.3 on end # - I2C 7
+ device pci 18.0 on end # - UART 0
+ device pci 18.1 off end # - UART 1
+ device pci 18.2 on end # - UART 2
+ device pci 18.3 off end # - UART 3
+ device pci 19.0 on end # - SPI 0
+ device pci 19.1 on end # - SPI 1
+ device pci 19.2 on end # - SPI 2
+ device pci 1a.0 on end # - PWM
+ device pci 1b.0 on end # - SDCARD
+ device pci 1c.0 on end # - eMMC
+ device pci 1e.0 off end # - SDIO
+ device pci 1f.0 on # - LPC
+ chip drivers/pc80/tpm
+ register "irq_polarity" = "2"
+ device pnp 0c31.0 on
+ irq 0x70 = 10
+ end
+ end
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end
+ device pci 1f.1 on end # - SMBUS
+ end
+end
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
new file mode 100644
index 0000000..bee5227
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
@@ -0,0 +1,296 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/*
+ * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'
+ * table found in EDS vol 1, but some pins aren't grouped functionally in
+ * the table so those were moved for more logical grouping.
+ */
+static const struct pad_config gpio_table[] = {
+/* NORTHWEST COMMUNITY GPIOS */
+ PAD_CFG_NF_NOIOS(GPIO_0, DN_20K, DEEP, NF1), /* TCK */
+ PAD_CFG_NF_NOIOS(GPIO_1, DN_20K, DEEP, NF1), /* TRST_B */
+ PAD_CFG_NF_NOIOS(GPIO_2, UP_20K, DEEP, NF1), /* TMS */
+ PAD_CFG_NF_NOIOS(GPIO_3, UP_20K, DEEP, NF1), /* TDI */
+ PAD_CFG_NF_NOIOS(GPIO_4, UP_20K, DEEP, NF1), /* TDO */
+ PAD_CFG_NF_NOIOS(GPIO_5, UP_20K, DEEP, NF1), /* JTAGX */
+ PAD_CFG_NF_NOIOS(GPIO_6, UP_20K, DEEP, NF1), /* CX_PREQ_B */
+ PAD_CFG_NF_NOIOS(GPIO_7, UP_20K, DEEP, NF1), /* CX_PRDY_B */
+ PAD_CFG_NF_IOS_3(GPIO_8, DN_20K, DEEP, NF5), /* TRACE_0_CLK_VNN */
+ PAD_CFG_NF_IOS_3(GPIO_9, DN_20K, DEEP, NF5), /* TRACE_0_DATA0_VNN */
+ PAD_CFG_NF_IOS_3(GPIO_10, DN_20K, DEEP, NF5), /* TRACE_0_DATA1_VNN */
+ PAD_CFG_NF_IOS_3(GPIO_11, DN_20K, DEEP, NF5), /* TRACE_0_DATA2_VNN */
+ PAD_CFG_NF_IOS_3(GPIO_12, DN_20K, DEEP, NF5), /* TRACE_0_DATA3_VNN */
+ PAD_CFG_NF_IOS_3(GPIO_13, DN_20K, DEEP, NF5), /* TRACE_0_DATA4_VNN */
+ PAD_CFG_NF_IOS_3(GPIO_14, DN_20K, DEEP, NF5), /* TRACE_0_DATA5_VNN */
+ PAD_CFG_NF_IOS_3(GPIO_15, DN_20K, DEEP, NF5), /* TRACE_0_DATA6_VNN */
+ PAD_CFG_NF_IOS_3(GPIO_16, DN_20K, DEEP, NF5), /* TRACE_0_DATA7_VNN */
+ PAD_CFG_GPO_1(GPIO_17, HI, DEEP, UP_20K, TxDRxE, SAME),/*Ec-to-SOC CS Wake */
+ PAD_CFG_GPI_APIC_IOS(GPIO_18, UP_20K, DEEP, LEVEL, NONE, IGNORE, SAME),/* Touch Pad Interrupt */
+ PAD_CFG_GPI_APIC_IOS(GPIO_19, UP_20K, DEEP, EDGE_SINGLE, NONE, TxDRxE, SAME),/*PMIC Interrupt*/
+ PAD_CFG_GPI_APIC_IOS(GPIO_20, NONE, DEEP, LEVEL, NONE, IGNORE, SAME),/* Audio Codec Interrupt*/
+ PAD_CFG_NF(GPIO_21, UP_20K, DEEP, NF2), /* CNV_MFUART2_RXD */
+ PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE), /* CNV_MFUART2_TXD */
+ PAD_CFG_NF(GPIO_23, UP_20K, DEEP, NF2), /* CNV_GNSS_PABLANKIt */
+ PAD_CFG_GPO_GPIO_DRIVER(GPIO_24, HI, DEEP, DN_20K),
+ PAD_CFG_GPO_1(GPIO_25, HI, DEEP, UP_20K, TxLASTRxE, SAME),/*WWAN /RF_KILL_GPS*/
+ PAD_CFG_NF_IOS_1(GPIO_26, UP_20K, DEEP, NF2),/* NFC Interrupt */
+ PAD_CFG_NF_IOS(GPIO_27, UP_20K, DEEP, NF2, TxLASTRxE, DISPUPD),/* RF_KILL_WiFi/WiFi_Disable */
+ PAD_CFG_GPO_1(GPIO_28, HI, DEEP, UP_20K, TxLASTRxE, DISPUPD),/* RF_KILL_BT/BT_Disable */
+ PAD_CFG_GPO_1(GPIO_29, HI, DEEP, UP_20K, HIZCRx0, DISPUPD),/* Codec Power Down: Ouput/ISH_GPIO_3*/
+ PAD_CFG_NF_NOIOS(GPIO_30, DN_20K, DEEP, NF1), /* ISH_GPIO_4 */
+ PAD_CFG_NF_NOIOS(GPIO_31, DN_20K, DEEP, NF1), /* ISH_GPIO_5 */
+ PAD_CFG_NF_NOIOS(GPIO_32, DN_20K, DEEP, NF1), /* ISH_GPIO_6 */
+ PAD_CFG_NF_NOIOS(GPIO_33, DN_20K, DEEP, NF1), /* ISH_GPIO_7 */
+ PAD_CFG_NF_NOIOS(GPIO_34, DN_20K, DEEP, NF1), /* ISH_GPIO_8/SUSCLK2 (1.8V) */
+ PAD_CFG_NF_NOIOS(GPIO_35, UP_20K, DEEP, NF6), /* BSSB_CLK */
+ PAD_CFG_NF_NOIOS(GPIO_36, UP_20K, DEEP, NF6), /* BSSB_DI */
+ PAD_CFG_GPI_SCI_IOS(GPIO_37, UP_20K, DEEP, EDGE_SINGLE, INVERT, IGNORE, SAME),/*Runtime SCI */
+ PAD_CFG_GPI_SCI_IOS(GPIO_38, UP_20K, DEEP, EDGE_SINGLE, NONE, IGNORE, SAME),/*Wake SCI */
+ PAD_CFG_GPI_APIC_IOS(GPIO_39, DN_20K, DEEP, LEVEL, NONE, IGNORE, SAME),/* Finger Print Sensor Interrupt (DRDY) */
+ PAD_CFG_NF_NOIOS(GPIO_40, UP_20K, DEEP, NF6),/*IERR (USB Camera Power Enable)*/
+ PAD_CFG_GPI_SMI_IOS(GPIO_41, UP_20K, DEEP, EDGE_SINGLE, NONE, IGNORE, SAME),/*SOC_EXTSMI_N */
+ PAD_CFG_NF(GPIO_42, DN_20K, DEEP, NF1), /* GP_INTD_DSI_TE1 */
+ PAD_CFG_NF(GPIO_43, DN_20K, DEEP, NF1), /* GP_INTD_DSI_TE2 */
+ PAD_CFG_NF(GPIO_44, UP_20K, DEEP, NF1), /* USB_OC0_B */
+ PAD_CFG_NF(GPIO_45, UP_20K, DEEP, NF1), /* USB_OC1_B */
+ PAD_CFG_NF_IOS_2(GPIO_46, DN_20K, DEEP, NF1), /* DSI_I2C_SDA */
+ PAD_CFG_NF_IOS_2(GPIO_47, UP_20K, DEEP, NF1), /* DSI_I2C_SCL */
+ PAD_CFG_NF_NOIOS(GPIO_48, UP_1K, DEEP, NF1), /* PMC_I2C_SDA */
+ PAD_CFG_NF_NOIOS(GPIO_49, UP_1K, DEEP, NF1), /* PMC_I2C_SCL */
+ PAD_CFG_NF_IOS_2(GPIO_50, UP_20K, DEEP, NF1), /* LPSS_I2C0_SDA - Audio Codec*/
+ PAD_CFG_NF_IOS_2(GPIO_51, UP_20K, DEEP, NF1), /* LPSS_I2C0_SCL - Audio Codec */
+ PAD_CFG_NF_IOS_2(GPIO_52, UP_20K, DEEP, NF1), /* LPSS_I2C1_SDA - NFC */
+ PAD_CFG_NF_IOS_2(GPIO_53, UP_20K, DEEP, NF1), /* LPSS_I2C1_SCL - NFC */
+ PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_54, UP_20K, DEEP, HIZCRx1, ENPU),/*LPSS_I2C2_SDA*/
+ PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_55, UP_20K, DEEP, HIZCRx1, ENPU),/*LPSS_I2C2_SCL*/
+ PAD_CFG_NF_IOS_2(GPIO_56, UP_20K, DEEP, NF1),/* I2C3-SDA - DBG (PSS, SINAI2, MIPI) */
+ PAD_CFG_NF_IOS_2(GPIO_57, UP_20K, DEEP, NF1),/*I2C3-SCL - DBG (PSS, SINAI2, MIPI) */
+ PAD_CFG_NF_IOS_2(GPIO_58, UP_20K, DEEP, NF1),/*I2C4-SDA - Touch Pad*/
+ PAD_CFG_NF_IOS_2(GPIO_59, UP_20K, DEEP, NF1),/*I2C4-SCL - Touch Pad*/
+ PAD_CFG_NF_IOS_1(GPIO_60, UP_20K, DEEP, NF1),/* UART0-RXD - M.2dGNSS */
+ PAD_CFG_NF_IOS_1(GPIO_61, UP_20K, DEEP, NF1),/* UART0-TXD - M.2dGNSS */
+ PAD_CFG_NF_IOS_1(GPIO_62, UP_20K, DEEP, NF1),/* UART0-RTS_B - M.2 dGNSS */
+ PAD_CFG_NF_IOS_1(GPIO_63, UP_20K, DEEP, NF1),/* UART0-CTS_B - M.2 dGNSS */
+ PAD_CFG_NF_IOS_1(GPIO_64, UP_20K, DEEP, NF1),/*LPSS_UART2_RXD*/
+ PAD_CFG_NF_IOS(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD),/*LPSS_UART2_TXD*/
+ PAD_CFG_GPO_1(GPIO_66, HI, DEEP, UP_20K, TxDRxE, DISPUPD),/*RF_KILL_WWAN */
+#if IS_ENABLED(CONFIG_TPM_ON_FAST_SPI)
+ PAD_CFG_GPI_APIC_GPIO_DRIVER(GPIO_67, UP_20K, DEEP, LEVEL, NONE, HIZCRx1, DISPUPD),/*SPI TPM Interrupt */
+#endif
+ PAD_CFG_NF(GPIO_68, UP_20K, DEEP, NF1),/*PMC_SPI_FS0*/
+ PAD_CFG_GPI_APIC(GPIO_69, DN_20K, DEEP, EDGE_SINGLE, NONE),/*SIM Detect*/
+ PAD_CFG_NF(GPIO_70, DN_20K, DEEP, NF1),/*PMC_SPI_FS2*/
+ PAD_CFG_NF(GPIO_71, DN_20K, DEEP, NF1),/*PMC_SPI_RXD*/
+ PAD_CFG_NF(GPIO_72, DN_20K, DEEP, NF1),/*PMC_SPI_TXD*/
+ PAD_CFG_NF(GPIO_73, DN_20K, DEEP, NF1),/*PMC_SPI_CLK*/
+ PAD_CFG_NF(GPIO_74, DN_20K, DEEP, NF1),/*THERMTRIP_B*/
+ PAD_CFG_NF_IOSSTATE(GPIO_75, UP_20K, DEEP, NF1, HIZCRx1),/*PROCHOT_B*/
+ PAD_CFG_NF_IOSSTATE(GPIO_211, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC_RST_B*/
+ PAD_CFG_GPI_APIC_IOS(GPIO_212, UP_20K, DEEP, LEVEL, NONE, HIZCRx0, SAME),/*Touch Panel Interrupt*/
+ PAD_CFG_GPO_1(GPIO_213, HI, DEEP, NONE, HIZCRx0, SAME),/*DNX LED - CSE owned*/
+ PAD_CFG_GPO_1(GPIO_214, HI, DEEP, NONE, HIZCRx0, SAME),/*LAN Isolate*/
+/* NORTH COMMUNITY GPIOS */
+ PAD_CFG_NF_NOIOS(GPIO_76, UP_20K, DEEP, NF1),/*SVID Alert*/
+ PAD_CFG_NF_NOIOS(GPIO_77, UP_20K, DEEP, NF1),/* SVID Data */
+ PAD_CFG_NF_NOIOS(GPIO_78, UP_20K, DEEP, NF1),/* SVID Clk */
+ PAD_CFG_NF_NOIOS(GPIO_79, NATIVE, DEEP, NF1),/* Finger Print Sensor */
+ PAD_CFG_NF_NOIOS(GPIO_80, NATIVE, DEEP, NF1),/* Finger Print Sensor CS */
+ PAD_CFG_NF_NOIOS(GPIO_81, NONE, DEEP, NF3),/* FST_SPI_CS2_B - TPM */
+ PAD_CFG_NF_NOIOS(GPIO_82, NATIVE, DEEP, NF1),/* Finger Print Sensor */
+ PAD_CFG_NF_NOIOS(GPIO_83, NATIVE, DEEP, NF1),/* Finger Print Sensor */
+ PAD_CFG_NF_IOSSTATE(GPIO_84, NONE, DEEP, NF3, HIZCRx1),/* SPI iTouch*/
+ PAD_CFG_NF_IOSSTATE(GPIO_85, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch CS*/
+ PAD_CFG_NF_IOSSTATE(GPIO_86, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch*/
+ PAD_CFG_NF_IOSSTATE(GPIO_87, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch*/
+ PAD_CFG_NF_IOSSTATE(GPIO_88, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch*/
+ PAD_CFG_NF_IOSSTATE(GPIO_89, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch*/
+ PAD_CFG_NF_NOIOS(GPIO_90, NATIVE, DEEP, NF1),/*Function 1: FST SPI Boot Flash CS*/
+ PAD_CFG_GPIO_HI_Z(GPIO_91, NATIVE, DEEP, IGNORE, SAME),/*FST_SPI_CS1_B*/
+ PAD_CFG_NF_NOIOS(GPIO_92, DN_20K, DEEP, NF1),/*FST_SPI_MOSI_IO0*/
+ PAD_CFG_NF_NOIOS(GPIO_93, NATIVE, DEEP, NF1),/*FST_SPI_MISO_IO1*/
+ PAD_CFG_NF_NOIOS(GPIO_94, NATIVE, DEEP, NF1),/*FST_SPI_IO2*/
+ PAD_CFG_NF_NOIOS(GPIO_95, NATIVE, DEEP, NF1),/*FST_SPI_IO3*/
+ PAD_CFG_NF_NOIOS(GPIO_96, NATIVE, DEEP, NF1),/*FST_SPI_CLK*/
+ PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1),/*FST_SPI_CLK_FB*/
+ PAD_CFG_NF_NOIOS(GPIO_98, NONE, DEEP, NF1),/*PMU_PLTRST_B*/
+ PAD_CFG_NF_NOIOS(GPIO_99, UP_20K, DEEP, NF1),/*PMU_PWRBTN_B*/
+ PAD_CFG_NF_NOIOS(GPIO_100, NONE, DEEP, NF1),/*PMU_SLP_S0_B*/
+ PAD_CFG_NF_NOIOS(GPIO_101, NONE, DEEP, NF1),/*PMU_SLP_S3_B*/
+ PAD_CFG_NF_NOIOS(GPIO_102, NONE, DEEP, NF1),/*PMU_SLP_S4_B*/
+ PAD_CFG_NF_NOIOS(GPIO_103, NONE, DEEP, NF1),/*SUSPWRDNACK*/
+ PAD_CFG_NF_NOIOS(GPIO_104, UP_20K, DEEP, NF1),/*EMMC_DNX_PWR_EN_B*/
+ PAD_CFG_GPO_1(GPIO_105, LO, DEEP, DN_20K, IGNORE, SAME),/*x4 Slot-2 Reset*/
+ PAD_CFG_NF_NOIOS(GPIO_106, UP_20K, DEEP, NF1),/*PMU_BATLOW_B*/
+ PAD_CFG_NF_NOIOS(GPIO_107, UP_20K, DEEP, NF1),/*PMU_RESETBUTTON_B*/
+ PAD_CFG_NF_NOIOS(GPIO_108, NONE, DEEP, NF1),/*PMU_SUSCLK*/
+ PAD_CFG_NF_NOIOS(GPIO_109, NONE, DEEP, NF1),/*SUS_STAT_B*/
+ PAD_CFG_NF_IOS_2(GPIO_110, UP_20K, DEEP, NF2),/*LPSS_I2C5_SDA*/
+ PAD_CFG_NF_IOS_2(GPIO_111, UP_20K, DEEP, NF2),/*LPSS_I2C5_SCL*/
+ PAD_CFG_NF_IOS_2(GPIO_112, UP_20K, DEEP, NF2),/*LPSS_I2C6_SDA*/
+ PAD_CFG_NF_IOS_2(GPIO_113, UP_20K, DEEP, NF2),/*LPSS_I2C6_SCL*/
+ PAD_CFG_NF_IOS_2(GPIO_114, UP_20K, DEEP, NF1),/*LPSS_I2C7_SDA*/
+ PAD_CFG_NF_IOS_2(GPIO_115, UP_20K, DEEP, NF1),/*LPSS_I2C7_SCL*/
+ PAD_CFG_NF_NOIOS(GPIO_116, UP_20K, DEEP, NF1),/*PCIE_WAKE0_B*/
+ PAD_CFG_NF_NOIOS(GPIO_117, UP_20K, DEEP, NF1),/*PCIE_WAKE1_B*/
+ PAD_CFG_NF_NOIOS(GPIO_118, UP_20K, DEEP, NF1),/*PCIE_WAKE2_B*/
+ PAD_CFG_NF_NOIOS(GPIO_119, UP_20K, DEEP, NF1),/*PCIE_WAKE3_B*/
+ PAD_CFG_NF_IOSSTATE(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1),/*PCIE_CLKREQ0_B*/
+ PAD_CFG_NF_IOSSTATE(GPIO_121, UP_20K, DEEP, NF1, HIZCRx1),/*PCIE_CLKREQ1_B*/
+ PAD_CFG_NF_IOSSTATE(GPIO_122, UP_20K, DEEP, NF1, HIZCRx1),/*PCIE_CLKREQ2_B*/
+ PAD_CFG_NF_IOSSTATE(GPIO_123, UP_20K, DEEP, NF1, HIZCRx1),/*PCIE_CLKREQ3_B*/
+ PAD_CFG_NF_IOSSTATE(GPIO_124, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI0_DDC_SDA*/
+ PAD_CFG_NF_IOSSTATE(GPIO_125, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI0_DDC_SCL*/
+ PAD_CFG_NF_IOSSTATE(GPIO_126, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI1_DDC_SDA*/
+ PAD_CFG_NF_IOSSTATE(GPIO_127, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI1_DDC_SCL*/
+ PAD_CFG_NF_IOSSTATE(GPIO_128, DN_20K, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_VDDEN*/
+ PAD_CFG_NF_IOSSTATE(GPIO_129, DN_20K, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_BKLTEN*/
+ PAD_CFG_NF_IOSSTATE(GPIO_130, DN_20K, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_BKLTCTL*/
+ PAD_CFG_NF_IOSSTATE(GPIO_131, DN_20K, DEEP, NF1, TxDRxE ),/*HV_DDI0_HPD*/
+ PAD_CFG_NF_IOSSTATE(GPIO_132, DN_20K, DEEP, NF1, TxDRxE ),/*HV_DDI1_HPD*/
+ PAD_CFG_NF_IOSSTATE(GPIO_133, DN_20K, DEEP, NF1, TxDRxE ),/*HV_EDP_HPD*/
+ PAD_CFG_GPO_1(GPIO_134, HI, DEEP, UP_20K, IGNORE, SAME),/*Slot-1 Power Enable*/
+ PAD_CFG_GPO_1(GPIO_135, HI, DEEP, UP_20K, IGNORE, SAME),/*Slot-2 Power Enable*/
+ PAD_CFG_GPO_1(GPIO_136, HI, DEEP, DN_20K, IGNORE, SAME),/*DGPU Power Select*/
+ PAD_CFG_GPO_1(GPIO_137, HI, DEEP, UP_20K, IGNORE, SAME),/*slot-1 Reset*/
+ PAD_CFG_NF_IOS_1(GPIO_138, UP_20K, DEEP, NF2),/*SATA_GP0 (DC RTD3 need)*/
+ PAD_CFG_NF_IOS(GPIO_139, UP_20K, DEEP, NF2, TxLASTRxE, DISPUPD),/*SATA_GP1 (ZPODD_DEV_DET)*/
+ PAD_CFG_NF(GPIO_140, UP_20K, DEEP, NF5),/*SATA_DEVSLP0 (DC DEV SLP)*/
+ PAD_CFG_NF_IOSSTATE(GPIO_141, UP_20K, DEEP, NF5, HIZCRx1),/*SATA_DEVSLP1 (ZPODD DEV ATN)*/
+ PAD_CFG_NF_IOSSTATE(GPIO_142, UP_20K, DEEP, NF5, HIZCRx1),/*SATA_LED*/
+ PAD_CFG_GPI_APIC_IOS(GPIO_143, DN_20K, DEEP, LEVEL, NONE, HIZCRx1, SAME),/*DGPU Power Ok*/
+ PAD_CFG_NF_IOSSTATE(GPIO_144, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_VDDEN*/
+ PAD_CFG_NF_IOSSTATE(GPIO_145, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_BKLTEN*/
+ PAD_CFG_NF_IOSSTATE(GPIO_146, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_BKLTCTL*/
+ PAD_CFG_NF(GPIO_147, UP_20K, DEEP, NF1),/*LPC_ILB_SERIRQ*/
+ PAD_CFG_NF_IOS_1(GPIO_148, NONE, DEEP, NF1),/*LPC_CLKOUT0*/
+ PAD_CFG_NF_IOS_1(GPIO_149, NONE, DEEP, NF1),/*LPC_CLKOUT1*/
+ PAD_CFG_NF_IOS_1(GPIO_150, UP_20K, DEEP, NF1),/*LPC_AD0*/
+ PAD_CFG_NF_IOS_1(GPIO_151, UP_20K, DEEP, NF1),/*LPC_AD1*/
+ PAD_CFG_NF_IOS_1(GPIO_152, UP_20K, DEEP, NF1),/*LPC_AD2*/
+ PAD_CFG_NF_IOS_1(GPIO_153, UP_20K, DEEP, NF1),/*LPC_AD3*/
+ PAD_CFG_NF_IOS_1(GPIO_154, UP_20K, DEEP, NF1),/*LPC_CLKRUNB*/
+ PAD_CFG_NF_IOS_1(GPIO_155, UP_20K, DEEP, NF1),/*LPC_FRAMEB*/
+ PAD_CFG_GPO_1(GPIO_157, HI, DEEP, UP_20K, IGNORE, SAME),/*WWAN_Reset/dGPS Reset*/
+ PAD_CFG_GPO_1(GPIO_158, LO, DEEP, DN_20K, IGNORE, SAME),/*NFC_DFU*/
+ PAD_CFG_GPO_1(GPIO_159, HI, DEEP, UP_20K, TxDRxE, ENPD),/*NFC reset*/
+ PAD_CFG_GPO_1(GPIO_160, HI, DEEP, UP_20K, IGNORE, SAME),/*MDSI reset*/
+ PAD_CFG_GPO_1(GPIO_161, HI, DEEP, UP_20K, IGNORE, SAME),/*Touch panel reset*/
+ PAD_CFG_GPO_1(GPIO_162, HI, DEEP, UP_20K, IGNORE, SAME),/*AVS_I2S1_BCLK*/
+ PAD_CFG_GPO_1(GPIO_163, HI, DEEP, UP_20K, IGNORE, SAME),/*M.2 WiFi Reset*/
+ PAD_CFG_GPO_1(GPIO_164, HI, DEEP, UP_20K, TxDRxE, ENPD),/*Touch Panel Power Enable*/
+ PAD_CFG_GPO_1(GPIO_165, HI, DEEP, UP_20K, IGNORE, SAME),/*WWAN PWR EN/Full card power off*/
+
+/* AUDIO COMMUNITY GPIOS*/
+
+ PAD_CFG_NF_IOSSTATE(GPIO_166, DN_20K, DEEP, NF1, HIZCRx1),/*AVS_HDA_BCLK*/
+ PAD_CFG_NF_IOSSTATE(GPIO_167, DN_20K, DEEP, NF1, HIZCRx1),/*AVS_HDA_WS_SYNC*/
+ PAD_CFG_NF_IOSSTATE(GPIO_168, DN_20K, DEEP, NF1, HIZCRx1),/*AVS_HDA_SDI*/
+ PAD_CFG_NF_IOSSTATE(GPIO_169, DN_20K, DEEP, NF1, HIZCRx1),/*AVS_HDA_SDO*/
+ PAD_CFG_NF_IOSSTATE(GPIO_170, DN_20K, DEEP, NF1, HIZCRx1),/*AVS_HDA_RSTB*/
+ PAD_CFG_NF_IOSSTATE(GPIO_171, DN_20K, DEEP, NF1, HIZCRx1),/*AVS_M_CLK_A1*/
+ PAD_CFG_NF_IOSSTATE(GPIO_172, DN_20K, DEEP, NF1, HIZCRx1),/*AVS_M_CLK_B1*/
+ PAD_CFG_NF_IOS(GPIO_173, DN_20K, DEEP, NF1, HIZCRx1, ENPD),/*AVS_M_DATA_1*/
+ PAD_CFG_NF_IOSSTATE(GPIO_174, DN_20K, DEEP, NF1, HIZCRx1),/*AVS_M_CLK_AB2*/
+ PAD_CFG_NF_IOS(GPIO_175, DN_20K, DEEP, NF1, HIZCRx1, ENPD),/*AVS_M_DATA_2*/
+
+/* SCC COMMUNITY GPIOS */
+ PAD_CFG_NF_NOIOS(GPIO_176, UP_20K, DEEP, NF1),/*SMB_ALERTB*/
+ PAD_CFG_NF_NOIOS(GPIO_177, UP_20K, DEEP, NF1),/*SMB_CLK*/
+ PAD_CFG_NF_NOIOS(GPIO_178, UP_20K, DEEP, NF1),/*SMB_DATA*/
+ PAD_CFG_NF_NOIOS(GPIO_187, DN_20K, DEEP, NF1),/*SDCARD_LVL_WP*/
+ PAD_CFG_NF_IOS_3(GPIO_179, DN_20K, DEEP, NF1),/*SDCARD_CLK*/
+ PAD_CFG_NF(GPIO_180, DN_20K, DEEP, NF1),/*SDCARD_CLK_FB*/
+ PAD_CFG_NF_IOS_1(GPIO_181, UP_20K, DEEP, NF1),/*SDCARD_D0*/
+ PAD_CFG_NF_IOS_1(GPIO_182, UP_20K, DEEP, NF1),/*SDCARD_D1*/
+ PAD_CFG_NF_IOS_1(GPIO_183, UP_20K, DEEP, NF1),/*SDCARD_D2*/
+ PAD_CFG_NF_IOS_1(GPIO_184, UP_20K, DEEP, NF1),/*SDCARD_D3*/
+ PAD_CFG_NF_IOS_1(GPIO_185, UP_20K, DEEP, NF1),/*SDCARD_CMD*/
+ PAD_CFG_GPI_GPIO_DRIVER(GPIO_186, NONE, DEEP),/*SDCARD_CD_B*/
+ PAD_CFG_GPO_1(GPIO_188, LO, DEEP, NONE, TxDRxE, SAME),/*SD Card*/
+ PAD_CFG_GPO_1(GPIO_210, HI, DEEP, UP_20K, HIZCRx0, DISPUPD),
+ PAD_CFG_NF_IOSSTATE(GPIO_189, DN_20K, DEEP, NF1, HIZCRx0),/*OSC_CLK_OUT_0*/
+ PAD_CFG_NF_IOSSTATE(GPIO_190, DN_20K, DEEP, NF1, HIZCRx0),/*OSC_CLK_OUT_1*/
+ PAD_CFG_NF_NOIOS(GPIO_191, NONE, DEEP, NF1),/*CNV_BRI_DT*/
+ PAD_CFG_NF_NOIOS(GPIO_192, UP_20K, DEEP, NF1),/*CNV_BRI_RSP*/
+ PAD_CFG_NF_NOIOS(GPIO_193, NONE, DEEP, NF1),/*CNV_RGI_DT*/
+ PAD_CFG_NF_NOIOS(GPIO_194, UP_20K, DEEP, NF1),/*CNV_RGI_RSP*/
+ PAD_CFG_NF_NOIOS(GPIO_195, NONE, DEEP, NF1),/*CNV_RF_RESET_B*/
+ PAD_CFG_NF_NOIOS(GPIO_196, NONE, DEEP, NF1),/*XTAL_CLKREQ*/
+ PAD_CFG_NF(GPIO_197, DN_20K, DEEP, NF1),/*SDIO_CLK_FB*/
+ PAD_CFG_NF_IOSSTATE(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0),/*EMMC0_CLK*/
+ PAD_CFG_NF(GPIO_199, DN_20K, DEEP, NF1),/*EMMC0_CLK_FB*/
+ PAD_CFG_NF_IOSSTATE(GPIO_200, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D0*/
+ PAD_CFG_NF_IOSSTATE(GPIO_201, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D1*/
+ PAD_CFG_NF_IOSSTATE(GPIO_202, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D2*/
+ PAD_CFG_NF_IOSSTATE(GPIO_203, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D3*/
+ PAD_CFG_NF_IOSSTATE(GPIO_204, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D4*/
+ PAD_CFG_NF_IOSSTATE(GPIO_205, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D5*/
+ PAD_CFG_NF_IOSSTATE(GPIO_206, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D6*/
+ PAD_CFG_NF_IOSSTATE(GPIO_207, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D7*/
+ PAD_CFG_NF_IOSSTATE(GPIO_208, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_CMD*/
+ PAD_CFG_NF_IOSSTATE(GPIO_209, DN_20K, DEEP, NF1, HIZCRx0),/*EMMC0_STROBE*/
+};
+
+const struct pad_config * __attribute__((weak)) variant_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
+
+/* GPIOs needed prior to ramstage. */
+static const struct pad_config early_gpio_table[] = {
+ PAD_CFG_NF_NOIOS(GPIO_177, UP_20K, DEEP, NF1), /* SMB_CLK */
+ PAD_CFG_NF_NOIOS(GPIO_178, UP_20K, DEEP, NF1), /* SMB_DATA */
+};
+
+const struct pad_config * __attribute__((weak))
+variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
+
+/* GPIO settings before entering sleep. */
+static const struct pad_config sleep_gpio_table[] = {
+#if 0
+ PAD_CFG_GPO(GPIO_150, 0, DEEP), /* NFC_RESET_ODL */
+ PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP), /* NFC_INT_L */
+#endif
+};
+
+const struct pad_config * __attribute__((weak))
+variant_sleep_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(sleep_gpio_table);
+ return sleep_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+#if 0
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME),
+ CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME),
+#endif
+};
+
+const struct cros_gpio * __attribute__((weak)) variant_cros_gpios(size_t *num)
+{
+ *num = ARRAY_SIZE(cros_gpios);
+ return cros_gpios;
+}
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/acpi/dptf.asl
new file mode 100644
index 0000000..8c18687
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/acpi/dptf.asl
@@ -0,0 +1,89 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE 80
+#define DPTF_CPU_CRITICAL 90
+#define DPTF_CPU_ACTIVE_AC0 90
+#define DPTF_CPU_ACTIVE_AC1 80
+#define DPTF_CPU_ACTIVE_AC2 70
+#define DPTF_CPU_ACTIVE_AC3 60
+#define DPTF_CPU_ACTIVE_AC4 50
+
+#define DPTF_TSR0_SENSOR_ID 0
+#define DPTF_TSR0_SENSOR_NAME "Battery"
+#define DPTF_TSR0_PASSIVE 48
+#define DPTF_TSR0_CRITICAL 70
+
+#define DPTF_TSR1_SENSOR_ID 1
+#define DPTF_TSR1_SENSOR_NAME "Ambient"
+#define DPTF_TSR1_PASSIVE 60
+#define DPTF_TSR1_CRITICAL 70
+
+#define DPTF_TSR2_SENSOR_ID 2
+#define DPTF_TSR2_SENSOR_NAME "Charger"
+#define DPTF_TSR2_PASSIVE 55
+#define DPTF_TSR2_CRITICAL 100
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */
+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
+ Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
+})
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 0 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+ /* Charger Effect on Temp Sensor 1 */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
+#endif
+
+ /* CPU Effect on Temp Sensor 1 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 2 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, /* Revision */
+ Package () { /* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 1600, /* PowerLimitMinimum */
+ 12000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 200 /* StepSize */
+ },
+ Package () { /* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 6000, /* PowerLimitMinimum */
+ 8000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 1000 /* StepSize */
+ }
+})
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h
new file mode 100644
index 0000000..f2be328
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef BASEBOARD_EC_H
+#define BASEBOARD_EC_H
+
+#include <ec/google/chromeec/ec_commands.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid or power button or key press */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+ (MAINBOARD_EC_S5_WAKE_EVENTS |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
+
+#endif
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
new file mode 100644
index 0000000..b3aa7e9
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef BASEBOARD_GPIO_H
+#define BASEBOARD_GPIO_H
+
+#include <soc/gpio.h>
+
+/*
+ * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
+ * which is North community
+ */
+#define EC_SCI_GPI 0x25 //GPIO_37
+
+/* EC SMI */
+#define EC_SMI_GPI GPIO_49
+
+#define GPE_EC_WAKE 0x26 //GPIO_38
+
+/* Write Protect and indication if EC is in RW code. */
+#define GPIO_PCH_WP GPIO_75
+#define GPIO_EC_IN_RW GPIO_41
+
+/* Memory SKU GPIOs. */
+#define MEM_CONFIG3 GPIO_45
+#define MEM_CONFIG2 GPIO_38
+#define MEM_CONFIG1 GPIO_102
+#define MEM_CONFIG0 GPIO_101
+
+#endif /* BASEBOARD_GPIO_H */
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h
new file mode 100644
index 0000000..9f2ed06
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef BASEBOARD_VARIANTS_H
+#define BASEBOARD_VARIANTS_H
+
+#include <soc/gpio.h>
+#include <soc/meminit.h>
+#include <stdint.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* Return the board id for the current variant board. */
+uint8_t variant_board_id(void);
+
+/* The next set of functions return the gpio table and fill in the number of
+ * entries for each table. */
+const struct pad_config *variant_gpio_table(size_t *num);
+const struct pad_config *variant_early_gpio_table(size_t *num);
+const struct pad_config *variant_sleep_gpio_table(size_t *num);
+
+/* Baseboard default swizzle. Can be reused if swizzle is same. */
+extern const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle;
+/* Return LPDDR4 configuration structure. */
+const struct lpddr4_cfg *variant_lpddr4_config(void);
+/* Return memory SKU for the board. */
+size_t variant_memory_sku(void);
+
+/* Return ChromeOS gpio table and fill in number of entries. */
+const struct cros_gpio *variant_cros_gpios(size_t *num);
+
+/* Seed the NHLT tables with the board specific information. */
+struct nhlt;
+void variant_nhlt_init(struct nhlt *nhlt);
+
+#endif /* BASEBOARD_VARIANTS_H */
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/memory.c b/src/mainboard/intel/glkrvp/variants/baseboard/memory.c
new file mode 100644
index 0000000..c8c5c3b
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/memory.c
@@ -0,0 +1,144 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/meminit.h>
+#include <variant/gpio.h>
+
+const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle = {
+ /* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */
+ .phys[LP4_PHYS_CH0A] = {
+ /* DQA[0:7] pins of LPDDR4 module. */
+ .dqs[LP4_DQS0] = { 6, 7, 5, 4, 3, 1, 0, 2 },
+ /* DQA[8:15] pins of LPDDR4 module. */
+ .dqs[LP4_DQS1] = { 12, 10, 11, 13, 14, 8, 9, 15 },
+ /* DQB[0:7] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS2] = { 16, 22, 23, 20, 18, 17, 19, 21 },
+ /* DQB[7:15] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS3] = { 30, 28, 29, 25, 24, 26, 27, 31 },
+ },
+ .phys[LP4_PHYS_CH0B] = {
+ /* DQA[0:7] pins of LPDDR4 module. */
+ .dqs[LP4_DQS0] = { 7, 3, 5, 2, 6, 0, 1, 4 },
+ /* DQA[8:15] pins of LPDDR4 module. */
+ .dqs[LP4_DQS1] = { 9, 14, 12, 13, 10, 11, 8, 15 },
+ /* DQB[0:7] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS2] = { 20, 22, 23, 16, 19, 17, 18, 21 },
+ /* DQB[7:15] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS3] = { 28, 24, 26, 27, 29, 30, 31, 25 },
+ },
+ .phys[LP4_PHYS_CH1A] = {
+ /* DQA[0:7] pins of LPDDR4 module. */
+ .dqs[LP4_DQS0] = { 2, 1, 6, 7, 5, 4, 3, 0 },
+ /* DQA[8:15] pins of LPDDR4 module. */
+ .dqs[LP4_DQS1] = { 11, 10, 8, 9, 12, 15, 13, 14 },
+ /* DQB[0:7] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS2] = { 17, 23, 19, 16, 21, 22, 20, 18 },
+ /* DQB[7:15] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS3] = { 31, 29, 26, 25, 28, 27, 24, 30 },
+ },
+ .phys[LP4_PHYS_CH1B] = {
+ /* DQA[0:7] pins of LPDDR4 module. */
+ .dqs[LP4_DQS0] = { 4, 3, 7, 5, 6, 1, 0, 2 },
+ /* DQA[8:15] pins of LPDDR4 module. */
+ .dqs[LP4_DQS1] = { 15, 9, 8, 11, 14, 13, 12, 10 },
+ /* DQB[0:7] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS2] = { 20, 23, 22, 21, 18, 19, 16, 17 },
+ /* DQB[7:15] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS3] = { 25, 28, 30, 31, 26, 27, 24, 29 },
+ },
+};
+
+static const struct lpddr4_sku skus[] = {
+ /*
+ * K4F6E304HB-MGCJ - both logical channels While the parts
+ * are listed at 16Gb there are 2 ranks per channel so indicate
+ * the deneisty as 8Gb per rank.
+ */
+ [0] = {
+ .speed = LP4_SPEED_2400,
+ .ch0_rank_density = LP4_8Gb_DENSITY,
+ .ch1_rank_density = LP4_8Gb_DENSITY,
+ .ch0_dual_rank = 1,
+ .ch1_dual_rank = 1,
+ .part_num = "K4F6E304HB-MGCJ",
+ },
+ /* K4F8E304HB-MGCJ - both logical channels */
+ [1] = {
+ .speed = LP4_SPEED_2400,
+ .ch0_rank_density = LP4_8Gb_DENSITY,
+ .ch1_rank_density = LP4_8Gb_DENSITY,
+ .part_num = "K4F8E304HB-MGCJ",
+ },
+ /*
+ * MT53B512M32D2NP-062WT:C - both logical channels. While the parts
+ * are listed at 16Gb there are 2 ranks per channel so indicate
+ * the deneisty as 8Gb per rank.
+ */
+ [2] = {
+ .speed = LP4_SPEED_2400,
+ .ch0_rank_density = LP4_8Gb_DENSITY,
+ .ch1_rank_density = LP4_8Gb_DENSITY,
+ .ch0_dual_rank = 1,
+ .ch1_dual_rank = 1,
+ .part_num = "MT53B512M32D2NP",
+ .disable_periodic_retraining = 1,
+ },
+ /* MT53B256M32D1NP-062 WT:C - both logical channels */
+ [3] = {
+ .speed = LP4_SPEED_2400,
+ .ch0_rank_density = LP4_8Gb_DENSITY,
+ .ch1_rank_density = LP4_8Gb_DENSITY,
+ .part_num = "MT53B256M32D1NP",
+ .disable_periodic_retraining = 1,
+ },
+ /*
+ * H9HCNNNBPUMLHR-NLE - both logical channels. While the parts
+ * are listed at 16Gb there are 2 ranks per channel so indicate the
+ * density as 8Gb per rank.
+ */
+ [4] = {
+ .speed = LP4_SPEED_2400,
+ .ch0_rank_density = LP4_8Gb_DENSITY,
+ .ch1_rank_density = LP4_8Gb_DENSITY,
+ .ch0_dual_rank = 1,
+ .ch1_dual_rank = 1,
+ .part_num = "H9HCNNNBPUMLHR",
+ },
+ /* H9HCNNN8KUMLHR-NLE - both logical channels */
+ [5] = {
+ .speed = LP4_SPEED_2400,
+ .ch0_rank_density = LP4_8Gb_DENSITY,
+ .ch1_rank_density = LP4_8Gb_DENSITY,
+ .part_num = "H9HCNNN8KUMLHR",
+ },
+};
+
+static const struct lpddr4_cfg lp4cfg = {
+ .skus = skus,
+ .num_skus = ARRAY_SIZE(skus),
+ .swizzle_config = &baseboard_lpddr4_swizzle,
+};
+
+const struct lpddr4_cfg * __attribute__((weak)) variant_lpddr4_config(void)
+{
+ return &lp4cfg;
+}
+
+size_t __attribute__((weak)) variant_memory_sku(void)
+{
+ return 0;
+}
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c b/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c
new file mode 100644
index 0000000..ef9ec6c
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <nhlt.h>
+#include <soc/nhlt.h>
+
+void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt)
+{
+ /* 2 Channel DMIC array. */
+ if (!nhlt_soc_add_dmic_array(nhlt, 2))
+ printk(BIOS_ERR, "Added 2CH DMIC array.\n");
+
+ /* Dialog for Headset codec.
+ * Headset codec is bi-directional but uses the same configuration
+ * settings for render and capture endpoints.
+ */
+ if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1))
+ printk(BIOS_ERR, "Added Dialog_7219 codec.\n");
+
+ /* MAXIM Smart Amps for left and right speakers. */
+ if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP5))
+ printk(BIOS_ERR, "Added Maxim_98357 codec.\n");
+}
diff --git a/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/acpi/dptf.asl b/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000..f3ff04b
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/acpi/dptf.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/acpi/dptf.asl>
diff --git a/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/ec.h b/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/ec.h
new file mode 100644
index 0000000..586f106
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/ec.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/gpio.h b/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/gpio.h
new file mode 100644
index 0000000..6d1ce5a
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/gpio.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif /* MAINBOARD_GPIO_H */
--
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Iab688aca6a4f5c5e32801215ba3a1a440e50fbef
Gerrit-PatchSet: 9
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Andrey Petrov <andrey.petrov at gmail.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik at intel.com>
Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein at intel.com>
Gerrit-Reviewer: Brenton Dong <brenton.m.dong at intel.com>
Gerrit-Reviewer: Han Lim Ng <nhlhanlim93 at gmail.com>
Gerrit-Reviewer: Marc Herbert <marc.herbert at intel.com>
Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi at intel.com>
Gerrit-Reviewer: Shaunak Saha <shaunak.saha at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
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