[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Bring in delta for GLK SOC
Hannah Williams (Code Review)
gerrit at coreboot.org
Mon May 15 17:42:23 CEST 2017
Hannah Williams has uploaded a new change for review. ( https://review.coreboot.org/19603 )
Change subject: soc/intel/apollolake: Bring in delta for GLK SOC
......................................................................
soc/intel/apollolake: Bring in delta for GLK SOC
Change-Id: I3e76726bb77f0277ab5776ae9d3d42b7eb389fe3
Signed-off-by: Hannah Williams <hannah.williams at intel.com>
Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/Makefile.inc
R src/soc/intel/apollolake/acpi/gpio_apl.asl
C src/soc/intel/apollolake/acpi/gpio_glk.asl
M src/soc/intel/apollolake/acpi/gpiolib.asl
R src/soc/intel/apollolake/acpi/lpc_apl.asl
A src/soc/intel/apollolake/acpi/lpc_glk.asl
R src/soc/intel/apollolake/acpi/lpss_apl.asl
A src/soc/intel/apollolake/acpi/lpss_glk.asl
M src/soc/intel/apollolake/acpi/southbridge.asl
M src/soc/intel/apollolake/bootblock/bootblock.c
M src/soc/intel/apollolake/chip.c
M src/soc/intel/apollolake/chip.h
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/apollolake/dsp.c
A src/soc/intel/apollolake/gpio_apl.c
A src/soc/intel/apollolake/gpio_glk.c
M src/soc/intel/apollolake/graphics.c
M src/soc/intel/apollolake/i2c.c
M src/soc/intel/apollolake/include/soc/cpu.h
M src/soc/intel/apollolake/include/soc/gpio.h
A src/soc/intel/apollolake/include/soc/gpio_apl.h
A src/soc/intel/apollolake/include/soc/gpio_glk.h
A src/soc/intel/apollolake/include/soc/pci_apl_ids.h
A src/soc/intel/apollolake/include/soc/pci_glk_ids.h
M src/soc/intel/apollolake/include/soc/pci_ids.h
M src/soc/intel/apollolake/include/soc/pcr_ids.h
M src/soc/intel/apollolake/lpc.c
M src/soc/intel/apollolake/lpc_lib.c
M src/soc/intel/apollolake/northbridge.c
M src/soc/intel/apollolake/p2sb.c
M src/soc/intel/apollolake/pmc.c
M src/soc/intel/apollolake/romstage.c
M src/soc/intel/apollolake/sd.c
M src/soc/intel/apollolake/uart_early.c
35 files changed, 1,754 insertions(+), 262 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/19603/18
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 5e800a3..6eb241a 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -3,6 +3,13 @@
help
Intel Apollolake support
+config SOC_INTEL_GLK
+ bool
+ default n
+ select SOC_INTEL_APOLLOLAKE
+ help
+ Intel GLK support
+
if SOC_INTEL_APOLLOLAKE
config CPU_SPECIFIC_OPTIONS
@@ -55,6 +62,7 @@
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_FAST_SPI
+ select SOC_INTEL_COMMON_BLOCK_GPIO
select SOC_INTEL_COMMON_BLOCK_ITSS
select SOC_INTEL_COMMON_BLOCK_LPSS
select SOC_INTEL_COMMON_BLOCK_PCR
@@ -219,6 +227,22 @@
help
Name of FMAP region to write IFWI.
+if SOC_INTEL_GLK
+config IFWI_FILE_NAME_RVP1
+ string "Path of file to write to IFWI region"
+ depends on NEED_IFWI
+ default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ifwi.bin"
+ help
+ Name of file to store in the IFWI region.
+
+config IFWI_FILE_NAME_RVP2
+ string "Path of file to write to IFWI region"
+ depends on NEED_IFWI
+ default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ifwi.bin"
+ help
+ Name of file to store in the IFWI region.
+
+endif
config IFWI_FILE_NAME
string "Path of file to write to IFWI region"
depends on NEED_IFWI
@@ -267,7 +291,8 @@
choice
prompt "Cache-as-ram implementation"
- default CAR_CQOS
+ default CAR_CQOS if !SOC_INTEL_GLK
+ default CAR_NEM if SOC_INTEL_GLK
help
This option allows you to select how cache-as-ram (CAR) is set up.
@@ -318,8 +343,10 @@
hex
default 0x100000
+if !SOC_INTEL_GLK
config IFD_CHIPSET
string
default "aplk"
+endif
endif
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 50d323f..845c47f 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -9,9 +9,12 @@
subdirs-y += ../../../cpu/x86/cache
bootblock-y += bootblock/bootblock.c
-bootblock-y += bootblock/bootblock.c
bootblock-y += car.c
-bootblock-y += gpio.c
+ifeq ($(CONFIG_SOC_INTEL_GLK),y)
+bootblock-y += gpio_glk.c
+else
+bootblock-y += gpio_apl.c
+endif
bootblock-y += heci.c
bootblock-y += lpc_lib.c
bootblock-y += mmap_boot.c
@@ -23,7 +26,11 @@
romstage-y += car.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
-romstage-y += gpio.c
+ifeq ($(CONFIG_SOC_INTEL_GLK),y)
+romstage-y += gpio_glk.c
+else
+romstage-y += gpio_apl.c
+endif
romstage-y += heci.c
romstage-y += i2c_early.c
romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
@@ -38,7 +45,11 @@
smm-y += mmap_boot.c
smm-y += pmutil.c
-smm-y += gpio.c
+ifeq ($(CONFIG_SOC_INTEL_GLK),y)
+smm-y += gpio_glk.c
+else
+smm-y += gpio_apl.c
+endif
smm-y += smihandler.c
smm-y += spi.c
smm-y += tsc_freq.c
@@ -47,10 +58,16 @@
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
ramstage-y += cpu.c
ramstage-y += chip.c
+ifeq ($(CONFIG_SOC_INTEL_GLK),n)
ramstage-y += cse.c
+endif
ramstage-y += elog.c
ramstage-y += dsp.c
-ramstage-y += gpio.c
+ifeq ($(CONFIG_SOC_INTEL_GLK),y)
+ramstage-y += gpio_glk.c
+else
+ramstage-y += gpio_apl.c
+endif
ramstage-y += graphics.c
ramstage-y += heci.c
ramstage-y += i2c.c
@@ -93,8 +110,12 @@
verstage-y += reset.c
verstage-y += spi.c
-CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
+ifeq ($(CONFIG_SOC_INTEL_GLK),y)
+CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/glk
+else
CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/apollolake
+endif
+CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
# Since FSP-M runs in CAR we need to relocate it to a specific address
$(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_M_ADDR)
@@ -116,7 +137,15 @@
# 1. Write ifwi.bin.tmp to coreboot.rom using CONFIG_IFWI_FMAP_NAME.
ifeq ($(CONFIG_NEED_IFWI),y)
files_added:: $(IFWITOOL)
+ifeq ($(CONFIG_SOC_INTEL_GLK),y)
+ifeq ($(CONFIG_IS_GLK_RVP_1),y)
+ $(IFWITOOL) $(CONFIG_IFWI_FILE_NAME_RVP1) create -f $(objcbfs)/ifwi.bin.tmp
+else
+ $(IFWITOOL) $(CONFIG_IFWI_FILE_NAME_RVP2) create -f $(objcbfs)/ifwi.bin.tmp
+endif
+else
$(IFWITOOL) $(CONFIG_IFWI_FILE_NAME) create -f $(objcbfs)/ifwi.bin.tmp
+endif
$(IFWITOOL) $(objcbfs)/ifwi.bin.tmp delete -n OBBP
$(IFWITOOL) $(objcbfs)/ifwi.bin.tmp replace -n IBBP -f $(objcbfs)/bootblock.bin -d -e IBBL
$(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_IFWI_FMAP_NAME) -f $(objcbfs)/ifwi.bin.tmp --fill-upward
diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio_apl.asl
similarity index 99%
rename from src/soc/intel/apollolake/acpi/gpio.asl
rename to src/soc/intel/apollolake/acpi/gpio_apl.asl
index ceba72b..db667a3 100644
--- a/src/soc/intel/apollolake/acpi/gpio.asl
+++ b/src/soc/intel/apollolake/acpi/gpio_apl.asl
@@ -14,7 +14,7 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-#include <soc/gpio_defs.h>
+#include <soc/gpio_apl.h>
#include <soc/pcr_ids.h>
#include "gpiolib.asl"
@@ -200,3 +200,4 @@
*/
Method(_L0F, 0) {}
}
+
diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio_glk.asl
similarity index 90%
copy from src/soc/intel/apollolake/acpi/gpio.asl
copy to src/soc/intel/apollolake/acpi/gpio_glk.asl
index ceba72b..4abb0b0 100644
--- a/src/soc/intel/apollolake/acpi/gpio.asl
+++ b/src/soc/intel/apollolake/acpi/gpio_glk.asl
@@ -14,50 +14,24 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-#include <soc/gpio_defs.h>
-#include <soc/pcr_ids.h>
+#include <soc/gpio_glk.h>
+
#include "gpiolib.asl"
+#include <intelblocks/pcr.h>
+#include <soc/pcr_ids.h>
+
+
+#define PAD_CFG0_TX_STATE (1 << 0)
scope (\_SB) {
Device (GPO0)
{
Name (_ADR, 0)
- Name (_HID, "INT3452")
- Name (_CID, "INT3452")
- Name (_DDN, "General Purpose Input/Output (GPIO) Controller - North" )
+ Name (_HID, "INT3453")
+ Name (_CID, "INT3453")
+ Name (_DDN, "General Purpose Input/Output (GPIO) Controller - NorthWest" )
Name (_UID, 1)
-
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
- {
- GPIO_BANK_INT
- }
- })
-
- Method (_CRS, 0x0, NotSerialized)
- {
- CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
- ShiftLeft (PID_GPIO_N, PCR_PORTID_SHIFT, Local0)
- Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS)
- Return (^RBUF)
- }
-
- Method (_STA, 0x0, NotSerialized)
- {
- Return(0xf)
- }
- }
-
- Device (GPO1)
- {
- Name (_ADR, 0)
- Name (_HID, "INT3452")
- Name (_CID, "INT3452")
- Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Northwest" )
- Name (_UID, 2)
Name (RBUF, ResourceTemplate ()
{
@@ -82,12 +56,43 @@
}
}
+ Device (GPO1)
+ {
+ Name (_ADR, 0)
+ Name (_HID, "INT3453")
+ Name (_CID, "INT3453")
+ Name (_DDN, "General Purpose Input/Output (GPIO) Controller - North" )
+ Name (_UID, 2)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
+ {
+ GPIO_BANK_INT
+ }
+ })
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
+ ShiftLeft (PID_GPIO_N, PCR_PORTID_SHIFT, Local0)
+ Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS)
+ Return (^RBUF)
+ }
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return(0xf)
+ }
+ }
+
Device (GPO2)
{
Name (_ADR, 0)
- Name (_HID, "INT3452")
- Name (_CID, "INT3452")
- Name (_DDN, "General Purpose Input/Output (GPIO) Controller - West" )
+ Name (_HID, "INT3453")
+ Name (_CID, "INT3453")
+ Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Audio" )
Name (_UID, 3)
Name (RBUF, ResourceTemplate ()
@@ -102,7 +107,7 @@
Method (_CRS, 0x0, NotSerialized)
{
CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
- ShiftLeft (PID_GPIO_W, PCR_PORTID_SHIFT, Local0)
+ ShiftLeft (PID_GPIO_AUDIO, PCR_PORTID_SHIFT, Local0)
Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS)
Return (^RBUF)
}
@@ -116,9 +121,9 @@
Device (GPO3)
{
Name (_ADR, 0)
- Name (_HID, "INT3452")
- Name (_CID, "INT3452")
- Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Southwest" )
+ Name (_HID, "INT3453")
+ Name (_CID, "INT3453")
+ Name (_DDN, "General Purpose Input/Output (GPIO) Controller - SCC" )
Name (_UID, 4)
Name (RBUF, ResourceTemplate ()
@@ -133,7 +138,7 @@
Method (_CRS, 0x0, NotSerialized)
{
CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
- ShiftLeft (PID_GPIO_SW, PCR_PORTID_SHIFT, Local0)
+ ShiftLeft (PID_GPIO_SCC, PCR_PORTID_SHIFT, Local0)
Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS)
Return (^RBUF)
}
@@ -200,3 +205,4 @@
*/
Method(_L0F, 0) {}
}
+
diff --git a/src/soc/intel/apollolake/acpi/gpiolib.asl b/src/soc/intel/apollolake/acpi/gpiolib.asl
index a4d4b00..19ff90d 100644
--- a/src/soc/intel/apollolake/acpi/gpiolib.asl
+++ b/src/soc/intel/apollolake/acpi/gpiolib.asl
@@ -64,7 +64,7 @@
}
Store (Arg1, TEMP)
}
-
+#if !IS_ENABLED(CONFIG_SOC_INTEL_GLK)
/* Get DW0 address of a given pad */
Method (GDW0, 0x2, Serialized)
{
@@ -81,7 +81,7 @@
Method (CHSA, 0x1, Serialized)
{
/* Arg0 - GPIO pad offset relative to the community */
- Add (HOSTSW_OWN_REG_BASE, Multiply (Divide (Arg0, 32), 4), Local1)
+ Add (HOSTSW_OWN_REG_0, Multiply (Divide (Arg0, 32), 4), Local1)
Return (Local1)
}
@@ -115,4 +115,5 @@
}
Store (Arg2, TEMP)
}
+#endif
}
diff --git a/src/soc/intel/apollolake/acpi/lpc.asl b/src/soc/intel/apollolake/acpi/lpc_apl.asl
similarity index 100%
rename from src/soc/intel/apollolake/acpi/lpc.asl
rename to src/soc/intel/apollolake/acpi/lpc_apl.asl
diff --git a/src/soc/intel/apollolake/acpi/lpc_glk.asl b/src/soc/intel/apollolake/acpi/lpc_glk.asl
new file mode 100644
index 0000000..40c491a
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/lpc_glk.asl
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel LPC Bus Device - 0:1f.0 */
+
+Device (LPCB)
+{
+ Name (_ADR, 0x001f0000)
+}
+
+ Device (HPET)
+ {
+ Name (_HID, EISAID("PNP0103"))
+ Name (_CID, 0x010CD041)
+
+ Method (_STA, 0) /* Device Status */
+ {
+ Return (0xf) /* Enable and show device */
+ }
+
+ Name(_CRS, ResourceTemplate()
+ {
+ Memory32Fixed(ReadOnly, 0xfed00000, 0x400)
+ })
+ }
+
+ Device (RTC) /* Real Time Clock */
+ {
+ Name (_HID, EISAID("PNP0B00"))
+ Name (_CRS, ResourceTemplate()
+ {
+ IO (Decode16, 0x70, 0x70, 1, 8)
+/*
+ * Disable as Windows doesn't like it, and systems don't seem to use it.
+ * IRQNoFlags() { 8 }
+ */
+ })
+ }
+
+ Device (TIMR) /* Intel 8254 timer */
+ {
+ Name(_HID, EISAID("PNP0100"))
+ Name(_CRS, ResourceTemplate()
+ {
+ IO (Decode16, 0x40, 0x40, 0x01, 0x04)
+ IO (Decode16, 0x50, 0x50, 0x10, 0x04)
+ IRQNoFlags() {0}
+ })
+ }
+
+
+ Device(PIC) /* 8259 Interrupt Controller */
+ {
+ Name(_HID,EISAID("PNP0000"))
+ Name(_CRS, ResourceTemplate()
+ {
+ IO (Decode16, 0x20, 0x20, 0x01, 0x02)
+ IO (Decode16, 0x24, 0x24, 0x01, 0x02)
+ IO (Decode16, 0x28, 0x28, 0x01, 0x02)
+ IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)
+ IO (Decode16, 0x30, 0x30, 0x01, 0x02)
+ IO (Decode16, 0x34, 0x34, 0x01, 0x02)
+ IO (Decode16, 0x38, 0x38, 0x01, 0x02)
+ IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)
+ IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)
+ IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)
+ IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)
+ IO (Decode16, 0xac, 0xac, 0x01, 0x02)
+ IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)
+ IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)
+ IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)
+ IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)
+ IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
+ IRQNoFlags () { 2 }
+ })
+ }
+
diff --git a/src/soc/intel/apollolake/acpi/lpss.asl b/src/soc/intel/apollolake/acpi/lpss_apl.asl
similarity index 100%
rename from src/soc/intel/apollolake/acpi/lpss.asl
rename to src/soc/intel/apollolake/acpi/lpss_apl.asl
diff --git a/src/soc/intel/apollolake/acpi/lpss_glk.asl b/src/soc/intel/apollolake/acpi/lpss_glk.asl
new file mode 100644
index 0000000..0d3204f
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/lpss_glk.asl
@@ -0,0 +1,159 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+scope (\_SB.PCI0) {
+
+ Method(LPD3, 0, Serialized) {
+ OperationRegion (PMCS, PCI_Config, 0x84, 0x4)
+ Field (PMCS, WordAcc, NoLock, Preserve) {
+ PMSR, 32, // 0x84, PMCSR - Power Management Control and Status
+ }
+ // dummy read PMCSR
+ Store (PMSR, Local0)
+ And (Local0, 1, Local0) // Dummy operation on Local0
+ }
+
+ /* LPIO1 PWM */
+ Device(PWM) {
+ Name (_ADR, 0x001A0000)
+ Name (_DDN, "Intel(R) PWM Controller")
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ }
+
+ /* LPIO1 HS-UART #1 */
+ Device(URT1) {
+ Name (_ADR, 0x00180000)
+ Name (_DDN, "Intel(R) HS-UART Controller #1")
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ }
+
+ /* LPIO1 HS-UART #2 */
+ Device(URT2) {
+ Name (_ADR, 0x00180001)
+ Name (_DDN, "Intel(R) HS-UART Controller #2")
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ }
+
+ /* LPIO1 HS-UART #3 */
+ Device(URT3) {
+ Name (_ADR, 0x00180002)
+ Name (_DDN, "Intel(R) HS-UART Controller #3")
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ }
+
+ /* LPIO1 HS-UART #4 */
+ Device(URT4) {
+ Name (_ADR, 0x00180003)
+ Name (_DDN, "Intel(R) HS-UART Controller #4")
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ }
+
+ /* LPIO1 SPI */
+ Device(SPI1) {
+ Name (_ADR, 0x00190000)
+ Name (_DDN, "Intel(R) SPI Controller #1")
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ }
+
+ /* LPIO1 SPI #2 */
+ Device(SPI2) {
+ Name (_ADR, 0x00190001)
+ Name (_DDN, "Intel(R) SPI Controller #2")
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ }
+
+ /* LPIO1 SPI #3 */
+ Device(SPI3) {
+ Name (_ADR, 0x00190002)
+ Name (_DDN, "Intel(R) SPI Controller #3")
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ }
+
+
+ /* LPIO2 I2C #0 */
+ Device(I2C0) {
+ Name (_ADR, 0x00160000)
+ Name (_DDN, "Intel(R) I2C Controller #0")
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ }
+
+ /* LPIO2 I2C #1 */
+ Device(I2C1) {
+ Name (_ADR, 0x00160001)
+ Name (_DDN, "Intel(R) I2C Controller #1")
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ }
+
+ /* LPIO2 I2C #2 */
+ Device(I2C2) {
+ Name (_ADR, 0x00160002)
+ Name (_DDN, "Intel(R) I2C Controller #2")
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ }
+
+ /* LPIO2 I2C #3 */
+ Device(I2C3) {
+ Name (_ADR, 0x00160003)
+ Name (_DDN, "Intel(R) I2C Controller #3")
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ }
+
+ /* LPIO2 I2C #4 */
+ Device(I2C4) {
+ Name (_ADR, 0x00170000)
+ Name (_DDN, "Intel(R) I2C Controller #4")
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ }
+
+ /* LPIO2 I2C #5 */
+ Device(I2C5) {
+ Name (_ADR, 0x00170001)
+ Name (_DDN, "Intel(R) I2C Controller #5")
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ }
+
+ /* LPIO2 I2C #6 */
+ Device(I2C6) {
+ Name (_ADR, 0x00170002)
+ Name (_DDN, "Intel(R) I2C Controller #6")
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ }
+
+ /* LPIO2 I2C #7 */
+ Device(I2C7) {
+ Name (_ADR, 0x00170003)
+ Name (_DDN, "Intel(R) I2C Controller #7")
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ }
+}
+
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index 823173f..02c2895 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -30,22 +30,38 @@
/* PCIE device */
#include "pcie.asl"
-/* LPSS device */
-#include "lpss.asl"
/* PCI IRQ assignment */
#include "pci_irqs.asl"
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+
+/* LPSS device */
+#include "lpss_glk.asl"
/* GPIO controller */
-#include "gpio.asl"
+#include "gpio_glk.asl"
+/* LPC */
+#include "lpc_glk.asl"
+
+#else
+
+/* LPSS device */
+#include "lpss_apl.asl"
+/* GPIO controller */
+#include "gpio_apl.asl"
+/* LPC */
+#include "lpc_apl.asl"
+#endif
#include "xhci.asl"
-/* LPC */
-#include "lpc.asl"
/* eMMC */
+#if !IS_ENABLED(CONFIG_SOC_INTEL_GLK)
#include "scs.asl"
+#else
+
+#endif
/* PMC IPC controller */
#include "pmc_ipc.asl"
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 2c98be4..8ebc396 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -35,7 +35,9 @@
#include <timestamp.h>
static const struct pad_config tpm_spi_configs[] = {
+#if !IS_ENABLED(CONFIG_SOC_INTEL_GLK)
PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */
+#endif
};
static void tpm_enable(void)
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 5211f84..50a285e 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -450,7 +450,9 @@
{
FSP_S_CONFIG *silconfig = &silupd->FspsConfig;
static struct soc_intel_apollolake_config *cfg;
+#if !IS_ENABLED(CONFIG_SOC_INTEL_GLK)
uint8_t port;
+#endif
/* Load VBT before devicetree-specific config. */
silconfig->GraphicsConfigPtr = (uintptr_t)vbt;
@@ -507,7 +509,7 @@
silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable;
/* Bios config lockdown Audio clk and power gate */
silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown;
-
+#if !IS_ENABLED(CONFIG_SOC_INTEL_GLK)
/* USB2 eye diagram settings per port */
for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) {
if (cfg->usb2eye[port].Usb20PerPortTxPeHalf != 0)
@@ -538,7 +540,18 @@
silconfig->PortUsb20HsNpreDrvSel[port] =
cfg->usb2eye[port].Usb20HsNpreDrvSel;
}
-
+#endif
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+{
+int i =0;
+ silconfig->Gmm = 0;
+ silconfig->HdaEnable = 0;
+ for(;i<6;i++){
+ silconfig->PcieRootPortEn[i]=0;
+ silconfig->PcieRpHotPlug[i]=0;
+ }
+}
+#endif
}
struct chip_operations soc_intel_apollolake_ops = {
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 3221be7..1d8fac3 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -19,7 +19,6 @@
#define _SOC_APOLLOLAKE_CHIP_H_
#include <soc/gpe.h>
-#include <soc/gpio_defs.h>
#include <soc/gpio.h>
#include <soc/intel/common/lpss_i2c.h>
#include <device/i2c.h>
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index ff300bc..63cf50f 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -79,6 +79,7 @@
static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_INTEL, CPUID_APOLLOLAKE_A0 },
{ X86_VENDOR_INTEL, CPUID_APOLLOLAKE_B0 },
+ { X86_VENDOR_INTEL, CPUID_GLK_A0 },
{ 0, 0 },
};
diff --git a/src/soc/intel/apollolake/dsp.c b/src/soc/intel/apollolake/dsp.c
index a2d21aa..ddd2ff8 100644
--- a/src/soc/intel/apollolake/dsp.c
+++ b/src/soc/intel/apollolake/dsp.c
@@ -25,8 +25,14 @@
.scan_bus = &scan_static_bus,
};
+static const unsigned short pci_device_ids[] = {
+ PCI_DEVICE_ID_APOLLOLAKE_AUDIO,
+ PCI_DEVICE_ID_GLK_AUDIO,
+ 0,
+};
+
static const struct pci_driver apollolake_dsp __pci_driver = {
.ops = &dsp_dev_ops,
.vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_APOLLOLAKE_AUDIO
+ .devices = pci_device_ids,
};
diff --git a/src/soc/intel/apollolake/gpio_apl.c b/src/soc/intel/apollolake/gpio_apl.c
new file mode 100644
index 0000000..db2e0ed
--- /dev/null
+++ b/src/soc/intel/apollolake/gpio_apl.c
@@ -0,0 +1,141 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <gpio.h>
+#include <intelblocks/gpio.h>
+#include <intelblocks/itss.h>
+#include <intelblocks/pcr.h>
+#include <soc/itss.h>
+#include <soc/pm.h>
+
+const struct pad_community apl_gpio_communities[] = {
+ {
+ .port = PID_GPIO_SW,
+ .first_pad = SW_OFFSET,
+ .last_pad = LPC_FRAMEB,
+ .num_gpi_regs = NUM_SW_GPI_REGS,
+ .gpi_offset = 0,
+ .name = "GPIO_GPE_SW",
+ }, {
+ .port = PID_GPIO_W,
+ .first_pad = W_OFFSET,
+ .last_pad = SUSPWRDNACK,
+ .num_gpi_regs = NUM_W_GPI_REGS,
+ .gpi_offset = NUM_SW_GPI_REGS,
+ .name = "GPIO_GPE_W",
+ }, {
+ .port = PID_GPIO_NW,
+ .first_pad = NW_OFFSET,
+ .last_pad = GPIO_123,
+ .num_gpi_regs = NUM_NW_GPI_REGS,
+ .gpi_offset = NUM_W_GPI_REGS + NUM_SW_GPI_REGS,
+ .name = "GPIO_GPE_NW",
+ }, {
+ .port = PID_GPIO_N,
+ .first_pad = N_OFFSET,
+ .last_pad = SVID0_CLK,
+ .num_gpi_regs = NUM_N_GPI_REGS,
+ .gpi_offset = NUM_NW_GPI_REGS + NUM_W_GPI_REGS
+ + NUM_SW_GPI_REGS,
+ .name = "GPIO_GPE_N",
+ }
+};
+
+const struct pad_community *soc_gpio_get_community(size_t
+ *num_communities)
+{
+ *num_communities = ARRAY_SIZE(apl_gpio_communities);
+ return apl_gpio_communities;
+}
+
+void soc_gpio_configure_itss(const struct pad_community *comm,
+ const struct pad_config *cfg,
+ uint16_t port, gpio_t pad_cfg_offset)
+{
+ /* No ITSS configuration in SMM. */
+ if (ENV_SMM)
+ return;
+
+ int irq;
+
+ /* Set up ITSS polarity if pad is routed to APIC.
+ *
+ * The ITSS takes only active high interrupt signals. Therefore,
+ * if the pad configuration indicates an inversion assume the
+ * intent is for the ITSS polarity. Before forwarding on the
+ * request to the APIC there's an inversion setting for how the
+ * signal is forwarded to the APIC. Honor the inversion setting
+ * in the GPIO pad configuration so that a hardware active low
+ * signal looks that way to the APIC (double inversion).
+ */
+ if (!(cfg->pad_config0 & PAD_CFG0_ROUTE_IOAPIC))
+ return;
+
+ irq = pcr_read32(port, pad_cfg_offset + sizeof(uint32_t));
+ irq &= PAD_CFG1_IRQ_MASK;
+ if (!irq) {
+ printk(BIOS_ERR, "GPIO %u doesn't support APIC routing,\n",
+ cfg->pad);
+ return;
+ }
+
+ itss_set_irq_polarity(irq, !!(cfg->pad_config0 & PAD_CFG0_RX_POL_INVERT));
+}
+
+const char *gpio_acpi_path(gpio_t gpio_num)
+{
+ const struct pad_community *comm = gpio_get_community(gpio_num);
+
+ switch (comm->port) {
+ case PID_GPIO_N:
+ return "\\_SB.GPO0";
+ case PID_GPIO_NW:
+ return "\\_SB.GPO1";
+ case PID_GPIO_W:
+ return "\\_SB.GPO2";
+ case PID_GPIO_SW:
+ return "\\_SB.GPO3";
+ }
+
+ return NULL;
+}
+
+/* Helper function to map PMC register groups to tier1 sci groups */
+int soc_gpe_route_to_gpio(int route)
+{
+ switch (route) {
+ case PMC_GPE_SW_31_0:
+ return GPIO_GPE_SW_31_0;
+ case PMC_GPE_SW_63_32:
+ return GPIO_GPE_SW_63_32;
+ case PMC_GPE_NW_31_0:
+ return GPIO_GPE_NW_31_0;
+ case PMC_GPE_NW_63_32:
+ return GPIO_GPE_NW_63_32;
+ case PMC_GPE_NW_95_64:
+ return GPIO_GPE_NW_95_64;
+ case PMC_GPE_N_31_0:
+ return GPIO_GPE_N_31_0;
+ case PMC_GPE_N_63_32:
+ return GPIO_GPE_N_63_32;
+ case PMC_GPE_W_31_0:
+ return GPIO_GPE_W_31_0;
+ default:
+ return -1;
+ }
+}
diff --git a/src/soc/intel/apollolake/gpio_glk.c b/src/soc/intel/apollolake/gpio_glk.c
new file mode 100644
index 0000000..5513e8b
--- /dev/null
+++ b/src/soc/intel/apollolake/gpio_glk.c
@@ -0,0 +1,133 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <gpio.h>
+#include <intelblocks/gpio.h>
+#include <intelblocks/itss.h>
+#include <intelblocks/pcr.h>
+#include <soc/itss.h>
+#include <soc/pm.h>
+
+const struct pad_community glk_gpio_communities[] = {
+ {
+ .port = PID_GPIO_AUDIO,
+ .first_pad = AUDIO_OFFSET,
+ .last_pad = GPIO_175,
+ .num_gpi_regs = NUM_AUDIO_GPI_REGS,
+ .gpi_offset = 0,
+ .name = "GPIO_AUDIO",
+ }, {
+ .port = PID_GPIO_N,
+ .first_pad = N_OFFSET,
+ .last_pad = GPIO_155,
+ .num_gpi_regs = NUM_N_GPI_REGS,
+ .gpi_offset = NUM_AUDIO_GPI_REGS,
+ .name = "GPIO_NORTH",
+ }, {
+ .port = PID_GPIO_NW,
+ .first_pad = NW_OFFSET,
+ .last_pad = GPIO_214,
+ .num_gpi_regs = NUM_NW_GPI_REGS,
+ .gpi_offset = NUM_AUDIO_GPI_REGS + NUM_AUDIO_GPI_REGS,
+ .name = "GPIO_NORTHWEST",
+ }, {
+ .port = PID_GPIO_SCC,
+ .first_pad = SCC_OFFSET,
+ .last_pad = GPIO_209,
+ .num_gpi_regs = NUM_SCC_GPI_REGS,
+ .gpi_offset = NUM_AUDIO_GPI_REGS + NUM_AUDIO_GPI_REGS +
+ NUM_NW_GPI_REGS,
+ .name = "GPIO_SCC",
+ },
+};
+
+const struct pad_community *soc_gpio_get_community(size_t
+ *num_communities)
+{
+ *num_communities = ARRAY_SIZE(glk_gpio_communities);
+ return glk_gpio_communities;
+}
+
+/* Number of DWx config registers can be different for different SOCs */
+uint16_t soc_gpio_get_pad_config_offset(const struct pad_community *comm,
+ gpio_t pad)
+{
+ return PAD_CFG_BASE + ((pad) * GPIO_DWx_SIZE(4));
+}
+
+void soc_gpio_configure_itss(const struct pad_community *comm,
+ const struct pad_config *cfg,
+ uint16_t port, gpio_t pad_cfg_offset)
+{
+
+ /* No ITSS configuration in SMM. */
+ if (ENV_SMM)
+ return;
+
+ int irq;
+
+ /* Set up ITSS polarity if pad is routed to APIC.
+ *
+ * The ITSS takes only active high interrupt signals. Therefore,
+ * if the pad configuration indicates an inversion assume the
+ * intent is for the ITSS polarity. Before forwarding on the
+ * request to the APIC there's an inversion setting for how the
+ * signal is forwarded to the APIC. Honor the inversion setting
+ * in the GPIO pad configuration so that a hardware active low
+ * signal looks that way to the APIC (double inversion).
+ */
+ if (!(cfg->pad_config0 & PAD_CFG0_ROUTE_IOAPIC))
+ return;
+
+ irq = pcr_read32(port, pad_cfg_offset + sizeof(uint32_t));
+ irq &= PAD_CFG1_IRQ_MASK;
+ if (!irq) {
+ printk(BIOS_ERR, "GPIO %u doesn't support APIC routing,\n",
+ cfg->pad);
+ return;
+ }
+ printk(BIOS_DEBUG,"irq: %d setting polarity: %d\n",
+ irq, !!(cfg->pad_config0 & PAD_CFG0_RX_POL_INVERT));
+ itss_set_irq_polarity(irq, !!(cfg->pad_config0 & PAD_CFG0_RX_POL_INVERT));
+}
+
+const char *gpio_acpi_path(gpio_t gpio_num)
+{
+ const struct pad_community *comm = gpio_get_community(gpio_num);
+
+ switch (comm->port) {
+ case PID_GPIO_NW:
+ return "\\_SB.GPO0";
+ case PID_GPIO_N:
+ return "\\_SB.GPO1";
+ case PID_GPIO_AUDIO:
+ return "\\_SB.GPO2";
+ case PID_GPIO_SCC:
+ return "\\_SB.GPO3";
+ }
+
+ return NULL;
+}
+
+/* Helper function to map PMC register groups to tier1 sci groups */
+int soc_gpe_route_to_gpio(int route)
+{
+ if ((route >= GPE_NW_31_0) && (route <= GPE_SCC_34_32))
+ return route;
+ return -1;
+}
diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c
index 9963d2c..4ebf659 100644
--- a/src/soc/intel/apollolake/graphics.c
+++ b/src/soc/intel/apollolake/graphics.c
@@ -93,6 +93,7 @@
static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_APOLLOLAKE_IGD_HD_505,
PCI_DEVICE_ID_APOLLOLAKE_IGD_HD_500,
+ PCI_DEVICE_ID_GLK_IGD,
0,
};
diff --git a/src/soc/intel/apollolake/i2c.c b/src/soc/intel/apollolake/i2c.c
index 9aadc78..475f852 100644
--- a/src/soc/intel/apollolake/i2c.c
+++ b/src/soc/intel/apollolake/i2c.c
@@ -104,6 +104,14 @@
PCI_DEVICE_ID_APOLLOLAKE_I2C5,
PCI_DEVICE_ID_APOLLOLAKE_I2C6,
PCI_DEVICE_ID_APOLLOLAKE_I2C7,
+ PCI_DEVICE_ID_GLK_I2C0,
+ PCI_DEVICE_ID_GLK_I2C1,
+ PCI_DEVICE_ID_GLK_I2C2,
+ PCI_DEVICE_ID_GLK_I2C3,
+ PCI_DEVICE_ID_GLK_I2C4,
+ PCI_DEVICE_ID_GLK_I2C5,
+ PCI_DEVICE_ID_GLK_I2C6,
+ PCI_DEVICE_ID_GLK_I2C7,
0,
};
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
index 3391597..a1b76b0 100644
--- a/src/soc/intel/apollolake/include/soc/cpu.h
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -31,6 +31,7 @@
#define CPUID_APOLLOLAKE_A0 0x506c8
#define CPUID_APOLLOLAKE_B0 0x506c9
+#define CPUID_GLK_A0 0x706a0
#define BASE_CLOCK_MHZ 100
diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h
index 85fc759..18aa9bd 100644
--- a/src/soc/intel/apollolake/include/soc/gpio.h
+++ b/src/soc/intel/apollolake/include/soc/gpio.h
@@ -1,8 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Intel Corp.
- * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ * Copyright (C) 2017 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -15,170 +14,13 @@
* GNU General Public License for more details.
*/
-#ifndef _SOC_APOLLOLAKE_GPIO_H_
-#define _SOC_APOLLOLAKE_GPIO_H_
+#ifndef _SOC_APL_GPIO_H_
+#define _SOC_APL_GPIO_H_
-#include <soc/gpio_defs.h>
-/* __ACPI__ guard is needed to ignore below code in ACPI/ASL compilation */
-#ifndef __ACPI__
-#include <types.h>
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#include <soc/gpio_glk.h>
+#else
+#include <soc/gpio_apl.h>
+#endif
-typedef uint32_t gpio_t;
-
-/*
- * Structure to represent GPI status for GPE and SMI. Use helper
- * functions for interrogating particular GPIs. Here the number of
- * array elements is total number of groups that can be present in all
- * the communities.
- */
-struct gpi_status {
- uint32_t grp[NUM_GPI_STATUS_REGS];
-};
-
-/*
- * Clear GPI SMI status and fill in the structure representing enabled
- * and set status.
- */
-void gpi_clear_get_smi_status(struct gpi_status *sts);
-
-/* Return 1 if gpio is set in the gpi_status struct. Otherwise 0. */
-int gpi_status_get(const struct gpi_status *sts, gpio_t gpi);
-
-#define PAD_FUNC(value) PAD_CFG0_MODE_##value
-#define PAD_RESET(value) PAD_CFG0_RESET_##value
-#define PAD_PULL(value) PAD_CFG1_PULL_##value
-#define PAD_IOSSTATE(value) PAD_CFG1_IOSSTATE_##value
-#define PAD_IOSTERM(value) PAD_CFG1_IOSTERM_##value
-#define PAD_IRQ_CFG(route, trig, inv) \
- (PAD_CFG0_ROUTE_##route | \
- PAD_CFG0_TRIG_##trig | \
- (PAD_CFG0_RX_POL_##inv))
-
-#define _PAD_CFG_STRUCT(__pad, __config0, __config1) \
- { \
- .pad = __pad, \
- .config0 = __config0, \
- .config1 = __config1, \
- }
-
-/* Native function configuration */
-#define PAD_CFG_NF(pad, pull, rst, func) \
- PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, TxLASTRxE)
-
-/* Native function configuration for standby state */
-#define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \
- PAD_CFG_NF_IOSSTATE_IOSTERM(pad,pull, rst, func, iosstate, SAME)
-
-#define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \
- _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
- PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
-
-/* General purpose output, no pullup/down. */
-#define PAD_CFG_GPO(pad, val, rst) \
- _PAD_CFG_STRUCT(pad, \
- PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \
- PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE))
-
-/* General purpose input */
-#define PAD_CFG_GPI(pad, pull, rst) \
- _PAD_CFG_STRUCT(pad, \
- PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
- PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE))
-
-/* General purpose input. The following macro sets the
- * Host Software Pad Ownership to GPIO Driver mode.
- */
-#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \
- _PAD_CFG_STRUCT(pad, \
- PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
- PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxLASTRxE))
-
-/* No Connect configuration for unused pad.
- * NC should be GPI with Term as PU20K, PD20K, NONE depending upon default Term
- */
-#define PAD_NC(pad, pull) PAD_CFG_GPI(pad, pull, DEEP)
-
-/* General purpose input, routed to APIC */
-#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \
- _PAD_CFG_STRUCT(pad, \
- PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
- PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \
- PAD_IOSSTATE(TxLASTRxE))
-
-/*
- * The following APIC macros assume the APIC will handle the filtering
- * on its own end. One just needs to pass an active high message into the
- * ITSS.
- */
-#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \
- PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, INVERT)
-
-#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \
- PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE)
-
-/* General purpose input, routed to SMI */
-#define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \
- _PAD_CFG_STRUCT(pad, \
- PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
- PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \
- PAD_IOSSTATE(TxLASTRxE))
-
-#define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \
- PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT)
-
-#define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \
- PAD_CFG_GPI_SMI(pad, pull, rst, trig, NONE)
-
-/* General purpose input, routed to SCI */
-#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \
- _PAD_CFG_STRUCT(pad, \
- PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
- PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
- PAD_IOSSTATE(TxLASTRxE))
-
-#define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \
- PAD_CFG_GPI_SCI(pad, pull, rst, trig, INVERT)
-
-#define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \
- PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE)
-
-/* General purpose input, routed to NMI */
-#define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \
- _PAD_CFG_STRUCT(pad, \
- PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
- PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \
- PAD_IOSSTATE(TxLASTRxE))
-
-struct pad_config {
- uint32_t config0;
- uint16_t config1;
- uint16_t pad;
-};
-
-/*
- * Configuration for raw pads. Some pads are designated as only special function
- * pins, and don't have an associated GPIO number, so we need to expose the raw
- * pad configuration functionality.
- */
-void gpio_configure_pad(const struct pad_config *cfg);
-void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads);
-
-/* Calculate GPIO DW0 address */
-void *gpio_dwx_address(const uint16_t pad);
-
-/* Get the port id of given pad */
-uint8_t gpio_get_pad_portid(const uint16_t pad);
-
-/*
- * Set the GPIO groups for the GPE blocks. The values from PMC register GPE_CFG
- * are passed which is then mapped to proper groups for MISCCFG. This basically
- * sets the MISCCFG register bits:
- * dw0 = gpe0_route[11:8]. This is ACPI GPE0b.
- * dw1 = gpe0_route[15:12]. This is ACPI GPE0c.
- * dw2 = gpe0_route[19:16]. This is ACPI GPE0d.
- */
-void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d);
-
-#endif /* __ACPI__ */
-
-#endif /* _SOC_APOLLOLAKE_GPIO_H_ */
+#endif
diff --git a/src/soc/intel/apollolake/include/soc/gpio_apl.h b/src/soc/intel/apollolake/include/soc/gpio_apl.h
new file mode 100644
index 0000000..f8b6c86
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/gpio_apl.h
@@ -0,0 +1,510 @@
+/*
+ * Definitions for the GPIO subsystem on Apollolake
+ *
+ * Placed in a separate file since some of these definitions can be used from
+ * assembly code
+ *
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 - 2017 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_APOLLOLAKE_GPIO_H_
+#define _SOC_APOLLOLAKE_GPIO_H_
+
+#include <soc/pcr_ids.h>
+#include <intelblocks/gpio.h>
+
+#define PAD_DW0_MASK (PAD_CFG0_TX_STATE | \
+ PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE | PAD_CFG0_MODE_MASK |\
+ PAD_CFG0_ROUTE_MASK | PAD_CFG0_RXTENCFG_MASK | \
+ PAD_CFG0_RXINV_MASK | PAD_CFG0_PREGFRXSEL | \
+ PAD_CFG0_TRIG_MASK | PAD_CFG0_RXRAW1_MASK | \
+ PAD_CFG0_RXPADSTSEL_MASK | PAD_CFG0_RESET_MASK)
+
+#define PAD_DW1_MASK (PAD_CFG1_IOSTERM_MASK | \
+ PAD_CFG1_PULL_MASK | \
+ PAD_CFG1_IOSSTATE_MASK)
+
+/* number of bits defining the mode */
+#define PAD_MODE_MASK 0x7
+
+/* IOSF port numbers for GPIO comminuties*/
+#define GPIO_SW 0xc0
+#define GPIO_S 0xc2
+#define GPIO_NW 0xc4
+#define GPIO_N 0xc5
+#define GPIO_W 0xc7
+
+/*
+ * Miscellaneous Configuration register(MISCCFG).These are community specific
+ * registers and are meant to house miscellaneous configuration fields per
+ * community. There are 8 GPIO groups: GPP_0 -> GPP_8 (Group 3 is absent)
+ */
+#define GPIO_MISCCFG 0x10 /* Miscellaneous Configuration offset */
+#define GPIO_GPE_SW_31_0 0 /* SOUTHWEST GPIO# 0 ~ 31 belong to GROUP0 */
+#define GPIO_GPE_SW_63_32 1 /* SOUTHWEST GPIO# 32 ~ 42 belong to GROUP1 */
+#define GPIO_GPE_W_31_0 2 /* WEST GPIO# 0 ~ 25 belong to GROUP2 */
+#define GPIO_GPE_NW_31_0 4 /* NORTHWEST GPIO# 0 ~ 17 belong to GROUP4 */
+#define GPIO_GPE_NW_63_32 5 /* NORTHWEST GPIO# 32 ~ 63 belong to GROUP5 */
+#define GPIO_GPE_NW_95_64 6 /* NORTHWEST GPIO# 64 ~ 76 belong to GROUP6 */
+#define GPIO_GPE_N_31_0 7 /* NORTH GPIO# 0 ~ 31 belong to GROUP7 */
+#define GPIO_GPE_N_63_32 8 /* NORTH GPIO# 32 ~ 61 belong to GROUP8 */
+
+#define GPIO_MAX_NUM_PER_GROUP 32
+
+
+/* Host Software Pad Ownership Register.
+ * The pins in the community are divided into 3 groups :
+ * GPIO 0 ~ 31, GPIO 32 ~ 63, GPIO 64 ~ 95
+ */
+#define HOSTSW_OWN_REG_0 0x80
+
+
+#define PAD_CFG_BASE 0x500
+#define PAD_CFG_OFFSET(pad) (PAD_CFG_BASE + ((pad) * 8))
+
+#define GPI_INT_EN_0 0x110
+
+#define GPI_SMI_STS_0 0x140
+#define GPI_SMI_EN_0 0x150
+#define GPI_SMI_STS_OFFSET(group) (GPI_SMI_STS_0 + ((group) * 4))
+#define GPI_SMI_EN_OFFSET(group) (GPI_SMI_EN_0 + ((group) * 4))
+
+#define NUM_N_PADS (PAD_N(SVID0_CLK) + 1)
+#define NUM_NW_PADS (PAD_NW(GPIO_123) + 1)
+#define NUM_W_PADS (PAD_W(SUSPWRDNACK) + 1)
+#define NUM_SW_PADS (PAD_SW(LPC_FRAMEB) + 1)
+
+#define NUM_N_GPI_REGS \
+ (ALIGN_UP(NUM_N_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_NW_GPI_REGS \
+ (ALIGN_UP(NUM_NW_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_W_GPI_REGS \
+ (ALIGN_UP(NUM_W_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_SW_GPI_REGS \
+ (ALIGN_UP(NUM_SW_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_GPI_STATUS_REGS (NUM_N_GPI_REGS + NUM_NW_GPI_REGS \
+ + NUM_W_GPI_REGS + NUM_SW_GPI_REGS)
+
+/* North community pads */
+#define GPIO_0 0
+#define GPIO_1 1
+#define GPIO_2 2
+#define GPIO_3 3
+#define GPIO_4 4
+#define GPIO_5 5
+#define GPIO_6 6
+#define GPIO_7 7
+#define GPIO_8 8
+#define GPIO_9 9
+#define GPIO_10 10
+#define GPIO_11 11
+#define GPIO_12 12
+#define GPIO_13 13
+#define GPIO_14 14
+#define GPIO_15 15
+#define GPIO_16 16
+#define GPIO_17 17
+#define GPIO_18 18
+#define GPIO_19 19
+#define GPIO_20 20
+#define GPIO_21 21
+#define GPIO_22 22
+#define GPIO_23 23
+#define GPIO_24 24
+#define GPIO_25 25
+#define GPIO_26 26
+#define GPIO_27 27
+#define GPIO_28 28
+#define GPIO_29 29
+#define GPIO_30 30
+#define GPIO_31 31
+#define GPIO_32 32
+#define GPIO_33 33
+#define GPIO_34 34
+#define GPIO_35 35
+#define GPIO_36 36
+#define GPIO_37 37
+#define GPIO_38 38
+#define GPIO_39 39
+#define GPIO_40 40
+#define GPIO_41 41
+#define GPIO_42 42
+#define GPIO_43 43
+#define GPIO_44 44
+#define GPIO_45 45
+#define GPIO_46 46
+#define GPIO_47 47
+#define GPIO_48 48
+#define GPIO_49 49
+#define GPIO_62 50
+#define GPIO_63 51
+#define GPIO_64 52
+#define GPIO_65 53
+#define GPIO_66 54
+#define GPIO_67 55
+#define GPIO_68 56
+#define GPIO_69 57
+#define GPIO_70 58
+#define GPIO_71 59
+#define GPIO_72 60
+#define GPIO_73 61
+#define TCK 62
+#define TRST_B 63
+#define TMS 64
+#define TDI 65
+#define CX_PMODE 66
+#define CX_PREQ_B 67
+#define JTAGX 68
+#define CX_PRDY_B 69
+#define TDO 70
+#define CNV_BRI_DT 71
+#define CNV_BRI_RSP 72
+#define CNV_RGI_DT 73
+#define CNV_RGI_RSP 74
+#define SVID0_ALERT_B 75
+#define SVID0_DATA 76
+#define SVID0_CLK 77
+
+/* Northwest community pads */
+#define GPIO_187 78
+#define GPIO_188 79
+#define GPIO_189 80
+#define GPIO_190 81
+#define GPIO_191 82
+#define GPIO_192 83
+#define GPIO_193 84
+#define GPIO_194 85
+#define GPIO_195 86
+#define GPIO_196 87
+#define GPIO_197 88
+#define GPIO_198 89
+#define GPIO_199 90
+#define GPIO_200 91
+#define GPIO_201 92
+#define GPIO_202 93
+#define GPIO_203 94
+#define GPIO_204 95
+#define PMC_SPI_FS0 96
+#define PMC_SPI_FS1 97
+#define PMC_SPI_FS2 98
+#define PMC_SPI_RXD 99
+#define PMC_SPI_TXD 100
+#define PMC_SPI_CLK 101
+#define PMIC_PWRGOOD 102
+#define PMIC_RESET_B 103
+#define GPIO_213 104
+#define GPIO_214 105
+#define GPIO_215 106
+#define PMIC_THERMTRIP_B 107
+#define PMIC_STDBY 108
+#define PROCHOT_B 109
+#define PMIC_I2C_SCL 110
+#define PMIC_I2C_SDA 111
+#define GPIO_74 112
+#define GPIO_75 113
+#define GPIO_76 114
+#define GPIO_77 115
+#define GPIO_78 116
+#define GPIO_79 117
+#define GPIO_80 118
+#define GPIO_81 119
+#define GPIO_82 120
+#define GPIO_83 121
+#define GPIO_84 122
+#define GPIO_85 123
+#define GPIO_86 124
+#define GPIO_87 125
+#define GPIO_88 126
+#define GPIO_89 127
+#define GPIO_90 128
+#define GPIO_91 129
+#define GPIO_92 130
+#define GPIO_97 131
+#define GPIO_98 132
+#define GPIO_99 133
+#define GPIO_100 134
+#define GPIO_101 135
+#define GPIO_102 136
+#define GPIO_103 137
+#define FST_SPI_CLK_FB 138
+#define GPIO_104 139
+#define GPIO_105 140
+#define GPIO_106 141
+#define GPIO_109 142
+#define GPIO_110 143
+#define GPIO_111 144
+#define GPIO_112 145
+#define GPIO_113 146
+#define GPIO_116 147
+#define GPIO_117 148
+#define GPIO_118 149
+#define GPIO_119 150
+#define GPIO_120 151
+#define GPIO_121 152
+#define GPIO_122 153
+#define GPIO_123 154
+
+/* West community pads */
+#define GPIO_124 155
+#define GPIO_125 156
+#define GPIO_126 157
+#define GPIO_127 158
+#define GPIO_128 159
+#define GPIO_129 160
+#define GPIO_130 161
+#define GPIO_131 162
+#define GPIO_132 163
+#define GPIO_133 164
+#define GPIO_134 165
+#define GPIO_135 166
+#define GPIO_136 167
+#define GPIO_137 168
+#define GPIO_138 169
+#define GPIO_139 170
+#define GPIO_146 171
+#define GPIO_147 172
+#define GPIO_148 173
+#define GPIO_149 174
+#define GPIO_150 175
+#define GPIO_151 176
+#define GPIO_152 177
+#define GPIO_153 178
+#define GPIO_154 179
+#define GPIO_155 180
+#define GPIO_209 181
+#define GPIO_210 182
+#define GPIO_211 183
+#define GPIO_212 184
+#define OSC_CLK_OUT_0 185
+#define OSC_CLK_OUT_1 186
+#define OSC_CLK_OUT_2 187
+#define OSC_CLK_OUT_3 188
+#define OSC_CLK_OUT_4 189
+#define PMU_AC_PRESENT 190
+#define PMU_BATLOW_B 191
+#define PMU_PLTRST_B 192
+#define PMU_PWRBTN_B 193
+#define PMU_RESETBUTTON_B 194
+#define PMU_SLP_S0_B 195
+#define PMU_SLP_S3_B 196
+#define PMU_SLP_S4_B 197
+#define PMU_SUSCLK 198
+#define PMU_WAKE_B 199
+#define SUS_STAT_B 200
+#define SUSPWRDNACK 201
+
+/* Southwest community pads */
+#define GPIO_205 202
+#define GPIO_206 203
+#define GPIO_207 204
+#define GPIO_208 205
+#define GPIO_156 206
+#define GPIO_157 207
+#define GPIO_158 208
+#define GPIO_159 209
+#define GPIO_160 210
+#define GPIO_161 211
+#define GPIO_162 212
+#define GPIO_163 213
+#define GPIO_164 214
+#define GPIO_165 215
+#define GPIO_166 216
+#define GPIO_167 217
+#define GPIO_168 218
+#define GPIO_169 219
+#define GPIO_170 220
+#define GPIO_171 221
+#define GPIO_172 222
+#define GPIO_179 223
+#define GPIO_173 224
+#define GPIO_174 225
+#define GPIO_175 226
+#define GPIO_176 227
+#define GPIO_177 228
+#define GPIO_178 229
+#define GPIO_186 230
+#define GPIO_182 231
+#define GPIO_183 232
+#define SMB_ALERTB 233
+#define SMB_CLK 234
+#define SMB_DATA 235
+#define LPC_ILB_SERIRQ 236
+#define LPC_CLKOUT0 237
+#define LPC_CLKOUT1 238
+#define LPC_AD0 239
+#define LPC_AD1 240
+#define LPC_AD2 241
+#define LPC_AD3 242
+#define LPC_CLKRUNB 243
+#define LPC_FRAMEB 244
+
+/* PERST_0 not defined */
+#define GPIO_PRT0_UDEF 0xFF
+
+#define TOTAL_PADS 245
+#define N_OFFSET GPIO_0
+#define NW_OFFSET GPIO_187
+#define W_OFFSET GPIO_124
+#define SW_OFFSET GPIO_205
+
+/* Macros for translating a global pad offset to a local offset */
+#define PAD_N(pad) (pad - N_OFFSET)
+#define PAD_NW(pad) (pad - NW_OFFSET)
+#define PAD_W(pad) (pad - W_OFFSET)
+#define PAD_SW(pad) (pad - SW_OFFSET)
+
+/* Linux names of the GPIO devices. */
+#define GPIO_COMM_N_NAME "INT3452:00"
+#define GPIO_COMM_NW_NAME "INT3452:01"
+#define GPIO_COMM_W_NAME "INT3452:02"
+#define GPIO_COMM_SW_NAME "INT3452:03"
+
+/* Default configurations */
+#define PAD_CFG0_DEFAULT_FUNC(x) (PAD_CFG0_RESET_DEEP \
+ | PAD_CFG0_MODE_FUNC(x))
+#define PAD_CFG0_DEFAULT_NATIVE PAD_CFG0_DEFAULT_FUNC(1)
+
+#define PAD_CFG1_DEFAULT_PULLUP PAD_CFG1_PULL_UP_20K
+#define PAD_CFG1_DEFAULT_NATIVE PAD_CFG1_PULL_NATIVE
+
+/*
+ * IOxAPIC IRQs for the GPIOs, overlap is expected as we encourage to use
+ * shared IRQ instead of direct IRQ, in case of overlapping, we can easily
+ * program one of the overlap to shared IRQ to avoid the conflict.
+ */
+
+/* NorthWest community pads */
+#define PMIC_I2C_SDA_IRQ 0x32
+#define GPIO_74_IRQ 0x33
+#define GPIO_75_IRQ 0x34
+#define GPIO_76_IRQ 0x35
+#define GPIO_77_IRQ 0x36
+#define GPIO_78_IRQ 0x37
+#define GPIO_79_IRQ 0x38
+#define GPIO_80_IRQ 0x39
+#define GPIO_81_IRQ 0x3A
+#define GPIO_82_IRQ 0x3B
+#define GPIO_83_IRQ 0x3C
+#define GPIO_84_IRQ 0x3D
+#define GPIO_85_IRQ 0x3E
+#define GPIO_86_IRQ 0x3F
+#define GPIO_87_IRQ 0x40
+#define GPIO_88_IRQ 0x41
+#define GPIO_89_IRQ 0x42
+#define GPIO_90_IRQ 0x43
+#define GPIO_91_IRQ 0x44
+#define GPIO_97_IRQ 0x49
+#define GPIO_98_IRQ 0x4A
+#define GPIO_99_IRQ 0x4B
+#define GPIO_100_IRQ 0x4C
+#define GPIO_101_IRQ 0x4D
+#define GPIO_102_IRQ 0x4E
+#define GPIO_103_IRQ 0x4F
+#define GPIO_104_IRQ 0x50
+#define GPIO_105_IRQ 0x51
+#define GPIO_106_IRQ 0x52
+#define GPIO_109_IRQ 0x54
+#define GPIO_110_IRQ 0x55
+#define GPIO_111_IRQ 0x56
+#define GPIO_112_IRQ 0x57
+#define GPIO_113_IRQ 0x58
+#define GPIO_116_IRQ 0x5B
+#define GPIO_117_IRQ 0x5C
+#define GPIO_118_IRQ 0x5D
+#define GPIO_119_IRQ 0x5E
+#define GPIO_120_IRQ 0x5F
+#define GPIO_121_IRQ 0x60
+#define GPIO_122_IRQ 0x61
+#define GPIO_123_IRQ 0x62
+
+/* North community pads */
+#define GPIO_0_IRQ 0x63
+#define GPIO_1_IRQ 0x64
+#define GPIO_2_IRQ 0x65
+#define GPIO_3_IRQ 0x66
+#define GPIO_4_IRQ 0x67
+#define GPIO_5_IRQ 0x68
+#define GPIO_6_IRQ 0x69
+#define GPIO_7_IRQ 0x6A
+#define GPIO_8_IRQ 0x6B
+#define GPIO_9_IRQ 0x6C
+#define GPIO_10_IRQ 0x6D
+#define GPIO_11_IRQ 0x6E
+#define GPIO_12_IRQ 0x6F
+#define GPIO_13_IRQ 0x70
+#define GPIO_14_IRQ 0x71
+#define GPIO_15_IRQ 0x72
+#define GPIO_16_IRQ 0x73
+#define GPIO_17_IRQ 0x74
+#define GPIO_18_IRQ 0x75
+#define GPIO_19_IRQ 0x76
+#define GPIO_20_IRQ 0x77
+#define GPIO_21_IRQ 0x32
+#define GPIO_22_IRQ 0x33
+#define GPIO_23_IRQ 0x34
+#define GPIO_24_IRQ 0x35
+#define GPIO_25_IRQ 0x36
+#define GPIO_26_IRQ 0x37
+#define GPIO_27_IRQ 0x38
+#define GPIO_28_IRQ 0x39
+#define GPIO_29_IRQ 0x3A
+#define GPIO_30_IRQ 0x3B
+#define GPIO_31_IRQ 0x3C
+#define GPIO_32_IRQ 0x3D
+#define GPIO_33_IRQ 0x3E
+#define GPIO_34_IRQ 0x3F
+#define GPIO_35_IRQ 0x40
+#define GPIO_36_IRQ 0x41
+#define GPIO_37_IRQ 0x42
+#define GPIO_38_IRQ 0x43
+#define GPIO_39_IRQ 0x44
+#define GPIO_40_IRQ 0x45
+#define GPIO_41_IRQ 0x46
+#define GPIO_42_IRQ 0x47
+#define GPIO_43_IRQ 0x48
+#define GPIO_44_IRQ 0x49
+#define GPIO_45_IRQ 0x4A
+#define GPIO_46_IRQ 0x4B
+#define GPIO_47_IRQ 0x4C
+#define GPIO_48_IRQ 0x4D
+#define GPIO_49_IRQ 0x4E
+#define GPIO_62_IRQ 0x5B
+#define GPIO_63_IRQ 0x5C
+#define GPIO_64_IRQ 0x5D
+#define GPIO_65_IRQ 0x5E
+#define GPIO_66_IRQ 0x5F
+#define GPIO_67_IRQ 0x60
+#define GPIO_68_IRQ 0x61
+#define GPIO_69_IRQ 0x62
+#define GPIO_70_IRQ 0x63
+#define GPIO_71_IRQ 0x64
+#define GPIO_72_IRQ 0x65
+#define GPIO_73_IRQ 0x66
+
+#define PAD_CFG_BASE 0x500
+
+
+#ifndef __ACPI__
+struct gpi_status {
+ uint32_t grp[NUM_GPI_STATUS_REGS];
+};
+
+#endif /* __ACPI__ */
+#endif /* _SOC_APOLLOLAKE_GPIO_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/gpio_glk.h b/src/soc/intel/apollolake/include/soc/gpio_glk.h
new file mode 100644
index 0000000..35102ca
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/gpio_glk.h
@@ -0,0 +1,366 @@
+/*
+ *
+ * Placed in a separate file since some of these definitions can be used from
+ * assembly code
+ *
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_GLK_GPIO_H_
+#define _SOC_GLK_GPIO_H_
+
+#include <soc/pcr_ids.h>
+#include <intelblocks/gpio.h>
+
+#define PAD_DW0_MASK (PAD_CFG0_TX_STATE | \
+ PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE | PAD_CFG0_MODE_MASK |\
+ PAD_CFG0_ROUTE_MASK | PAD_CFG0_RXTENCFG_MASK | \
+ PAD_CFG0_RXINV_MASK | PAD_CFG0_PREGFRXSEL | \
+ PAD_CFG0_TRIG_MASK | PAD_CFG0_RXRAW1_MASK | \
+ PAD_CFG0_RXPADSTSEL_MASK | PAD_CFG0_RESET_MASK)
+
+#define PAD_DW1_MASK (PAD_CFG1_IOSTERM_MASK | \
+ PAD_CFG1_PULL_MASK | \
+ PAD_CFG1_IOSSTATE_MASK)
+
+/* North West community pads */
+/* For DFx GPIO, Display, USB, I2C, UART, and Thermal GPIO*/
+#define NW_OFFSET 0
+#define GPIO_0 (NW_OFFSET + 0)
+#define GPIO_1 (NW_OFFSET + 1)
+#define GPIO_2 (NW_OFFSET + 2)
+#define GPIO_3 (NW_OFFSET + 3)
+#define GPIO_4 (NW_OFFSET + 4)
+#define GPIO_5 (NW_OFFSET + 5)
+#define GPIO_6 (NW_OFFSET + 6)
+#define GPIO_7 (NW_OFFSET + 7)
+#define GPIO_8 (NW_OFFSET + 8)
+#define GPIO_9 (NW_OFFSET + 9)
+#define GPIO_10 (NW_OFFSET + 10)
+#define GPIO_11 (NW_OFFSET + 11)
+#define GPIO_12 (NW_OFFSET + 12)
+#define GPIO_13 (NW_OFFSET + 13)
+#define GPIO_14 (NW_OFFSET + 14)
+#define GPIO_15 (NW_OFFSET + 15)
+#define GPIO_16 (NW_OFFSET + 16)
+#define GPIO_17 (NW_OFFSET + 17)
+#define GPIO_18 (NW_OFFSET + 18)
+#define GPIO_19 (NW_OFFSET + 19)
+#define GPIO_20 (NW_OFFSET + 20)
+#define GPIO_21 (NW_OFFSET + 21)
+#define GPIO_22 (NW_OFFSET + 22)
+#define GPIO_23 (NW_OFFSET + 23)
+#define GPIO_24 (NW_OFFSET + 24)
+#define GPIO_25 (NW_OFFSET + 25)
+#define GPIO_26 (NW_OFFSET + 26)
+#define GPIO_27 (NW_OFFSET + 27)
+#define GPIO_28 (NW_OFFSET + 28)
+#define GPIO_29 (NW_OFFSET + 29)
+#define GPIO_30 (NW_OFFSET + 30)
+#define GPIO_31 (NW_OFFSET + 31)
+#define GPIO_32 (NW_OFFSET + 32)
+#define GPIO_33 (NW_OFFSET + 33)
+#define GPIO_34 (NW_OFFSET + 34)
+#define GPIO_35 (NW_OFFSET + 35)
+#define GPIO_36 (NW_OFFSET + 36)
+#define GPIO_37 (NW_OFFSET + 37)
+#define GPIO_38 (NW_OFFSET + 38)
+#define GPIO_39 (NW_OFFSET + 39)
+#define GPIO_40 (NW_OFFSET + 40)
+#define GPIO_41 (NW_OFFSET + 41)
+#define GPIO_42 (NW_OFFSET + 42)
+#define GPIO_43 (NW_OFFSET + 43)
+#define GPIO_44 (NW_OFFSET + 44)
+#define GPIO_45 (NW_OFFSET + 45)
+#define GPIO_46 (NW_OFFSET + 46)
+#define GPIO_47 (NW_OFFSET + 47)
+#define GPIO_48 (NW_OFFSET + 48)
+#define GPIO_49 (NW_OFFSET + 49)
+#define GPIO_50 (NW_OFFSET + 50)
+#define GPIO_51 (NW_OFFSET + 51)
+#define GPIO_52 (NW_OFFSET + 52)
+#define GPIO_53 (NW_OFFSET + 53)
+#define GPIO_54 (NW_OFFSET + 54)
+#define GPIO_55 (NW_OFFSET + 55)
+#define GPIO_56 (NW_OFFSET + 56)
+#define GPIO_57 (NW_OFFSET + 57)
+#define GPIO_58 (NW_OFFSET + 58)
+#define GPIO_59 (NW_OFFSET + 59)
+#define GPIO_60 (NW_OFFSET + 60)
+#define GPIO_61 (NW_OFFSET + 61)
+#define GPIO_62 (NW_OFFSET + 62)
+#define GPIO_63 (NW_OFFSET + 63)
+#define GPIO_64 (NW_OFFSET + 64)
+#define GPIO_65 (NW_OFFSET + 65)
+#define GPIO_66 (NW_OFFSET + 66)
+#define GPIO_67 (NW_OFFSET + 67)
+#define GPIO_68 (NW_OFFSET + 68)
+#define GPIO_69 (NW_OFFSET + 69)
+#define GPIO_70 (NW_OFFSET + 70)
+#define GPIO_71 (NW_OFFSET + 71)
+#define GPIO_72 (NW_OFFSET + 72)
+#define GPIO_73 (NW_OFFSET + 73)
+#define GPIO_74 (NW_OFFSET + 74)
+#define GPIO_75 (NW_OFFSET + 75)
+#define GPIO_211 (NW_OFFSET + 76)
+#define GPIO_212 (NW_OFFSET + 77)
+#define GPIO_213 (NW_OFFSET + 78)
+#define GPIO_214 (NW_OFFSET + 79)
+#define TOTAL_NW_PADS 80
+
+/* North Community Pads */
+/* For power management GPIO, I2C, Display, LPC/eSPI, SPI */
+#define N_OFFSET (NW_OFFSET + 80)
+#define GPIO_76 (N_OFFSET + 0)
+#define GPIO_77 (N_OFFSET + 1)
+#define GPIO_78 (N_OFFSET + 2)
+#define GPIO_79 (N_OFFSET + 3)
+#define GPIO_80 (N_OFFSET + 4)
+#define GPIO_81 (N_OFFSET + 5)
+#define GPIO_82 (N_OFFSET + 6)
+#define GPIO_83 (N_OFFSET + 7)
+#define GPIO_84 (N_OFFSET + 8)
+#define GPIO_85 (N_OFFSET + 9)
+#define GPIO_86 (N_OFFSET + 10)
+#define GPIO_87 (N_OFFSET + 11)
+#define GPIO_88 (N_OFFSET + 12)
+#define GPIO_89 (N_OFFSET + 13)
+#define GPIO_90 (N_OFFSET + 14)
+#define GPIO_91 (N_OFFSET + 15)
+#define GPIO_92 (N_OFFSET + 16)
+#define GPIO_93 (N_OFFSET + 17)
+#define GPIO_94 (N_OFFSET + 18)
+#define GPIO_95 (N_OFFSET + 19)
+#define GPIO_96 (N_OFFSET + 20)
+#define GPIO_97 (N_OFFSET + 21)
+#define GPIO_98 (N_OFFSET + 22)
+#define GPIO_99 (N_OFFSET + 23)
+#define GPIO_100 (N_OFFSET + 24)
+#define GPIO_101 (N_OFFSET + 25)
+#define GPIO_102 (N_OFFSET + 26)
+#define GPIO_103 (N_OFFSET + 27)
+#define GPIO_104 (N_OFFSET + 28)
+#define GPIO_105 (N_OFFSET + 29)
+#define GPIO_106 (N_OFFSET + 30)
+#define GPIO_107 (N_OFFSET + 31)
+#define GPIO_108 (N_OFFSET + 32)
+#define GPIO_109 (N_OFFSET + 33)
+#define GPIO_110 (N_OFFSET + 34)
+#define GPIO_111 (N_OFFSET + 35)
+#define GPIO_112 (N_OFFSET + 36)
+#define GPIO_113 (N_OFFSET + 37)
+#define GPIO_114 (N_OFFSET + 38)
+#define GPIO_115 (N_OFFSET + 39)
+#define GPIO_116 (N_OFFSET + 40)
+#define GPIO_117 (N_OFFSET + 41)
+#define GPIO_118 (N_OFFSET + 42)
+#define GPIO_119 (N_OFFSET + 43)
+#define GPIO_120 (N_OFFSET + 44)
+#define GPIO_121 (N_OFFSET + 45)
+#define GPIO_122 (N_OFFSET + 46)
+#define GPIO_123 (N_OFFSET + 47)
+#define GPIO_124 (N_OFFSET + 48)
+#define GPIO_125 (N_OFFSET + 49)
+#define GPIO_126 (N_OFFSET + 50)
+#define GPIO_127 (N_OFFSET + 51)
+#define GPIO_128 (N_OFFSET + 52)
+#define GPIO_129 (N_OFFSET + 53)
+#define GPIO_130 (N_OFFSET + 54)
+#define GPIO_131 (N_OFFSET + 55)
+#define GPIO_132 (N_OFFSET + 56)
+#define GPIO_133 (N_OFFSET + 57)
+#define GPIO_134 (N_OFFSET + 58)
+#define GPIO_135 (N_OFFSET + 59)
+#define GPIO_136 (N_OFFSET + 60)
+#define GPIO_137 (N_OFFSET + 61)
+#define GPIO_138 (N_OFFSET + 62)
+#define GPIO_139 (N_OFFSET + 63)
+#define GPIO_140 (N_OFFSET + 64)
+#define GPIO_141 (N_OFFSET + 65)
+#define GPIO_142 (N_OFFSET + 66)
+#define GPIO_143 (N_OFFSET + 67)
+#define GPIO_144 (N_OFFSET + 68)
+#define GPIO_145 (N_OFFSET + 69)
+#define GPIO_146 (N_OFFSET + 70)
+#define GPIO_147 (N_OFFSET + 71)
+#define GPIO_148 (N_OFFSET + 72)
+#define GPIO_149 (N_OFFSET + 73)
+#define GPIO_150 (N_OFFSET + 74)
+#define GPIO_151 (N_OFFSET + 75)
+#define GPIO_152 (N_OFFSET + 76)
+#define GPIO_153 (N_OFFSET + 77)
+#define GPIO_154 (N_OFFSET + 78)
+#define GPIO_155 (N_OFFSET + 79)
+#define TOTAL_N_PADS 80
+
+/* Audio Community Pads */
+#define AUDIO_OFFSET (N_OFFSET + 80)
+#define GPIO_156 (AUDIO_OFFSET + 0)
+#define GPIO_157 (AUDIO_OFFSET + 1)
+#define GPIO_158 (AUDIO_OFFSET + 2)
+#define GPIO_159 (AUDIO_OFFSET + 3)
+#define GPIO_160 (AUDIO_OFFSET + 4)
+#define GPIO_161 (AUDIO_OFFSET + 5)
+#define GPIO_162 (AUDIO_OFFSET + 6)
+#define GPIO_163 (AUDIO_OFFSET + 7)
+#define GPIO_164 (AUDIO_OFFSET + 8)
+#define GPIO_165 (AUDIO_OFFSET + 9)
+#define GPIO_166 (AUDIO_OFFSET + 10)
+#define GPIO_167 (AUDIO_OFFSET + 11)
+#define GPIO_168 (AUDIO_OFFSET + 12)
+#define GPIO_169 (AUDIO_OFFSET + 13)
+#define GPIO_170 (AUDIO_OFFSET + 14)
+#define GPIO_171 (AUDIO_OFFSET + 15)
+#define GPIO_172 (AUDIO_OFFSET + 16)
+#define GPIO_173 (AUDIO_OFFSET + 17)
+#define GPIO_174 (AUDIO_OFFSET + 18)
+#define GPIO_175 (AUDIO_OFFSET + 19)
+#define TOTAL_AUDIO_PADS 20
+
+
+/* SCC community pads */
+/* For SMBus, SD-Card, Clock, CNV/SDIO, eMMC */
+#define SCC_OFFSET (AUDIO_OFFSET + 20)
+#define GPIO_176 (SCC_OFFSET + 0)
+#define GPIO_177 (SCC_OFFSET + 1)
+#define GPIO_178 (SCC_OFFSET + 2)
+#define GPIO_187 (SCC_OFFSET + 3)
+#define GPIO_179 (SCC_OFFSET + 4)
+#define GPIO_180 (SCC_OFFSET + 5)
+#define GPIO_181 (SCC_OFFSET + 6)
+#define GPIO_182 (SCC_OFFSET + 7)
+#define GPIO_183 (SCC_OFFSET + 8)
+#define GPIO_184 (SCC_OFFSET + 9)
+#define GPIO_185 (SCC_OFFSET + 10)
+#define GPIO_186 (SCC_OFFSET + 11)
+#define GPIO_188 (SCC_OFFSET + 12)
+#define GPIO_210 (SCC_OFFSET + 13)
+#define GPIO_189 (SCC_OFFSET + 14)
+#define GPIO_190 (SCC_OFFSET + 15)
+#define GPIO_191 (SCC_OFFSET + 16)
+#define GPIO_192 (SCC_OFFSET + 17)
+#define GPIO_193 (SCC_OFFSET + 18)
+#define GPIO_194 (SCC_OFFSET + 19)
+#define GPIO_195 (SCC_OFFSET + 20)
+#define GPIO_196 (SCC_OFFSET + 21)
+#define GPIO_197 (SCC_OFFSET + 22)
+#define GPIO_198 (SCC_OFFSET + 23)
+#define GPIO_199 (SCC_OFFSET + 24)
+#define GPIO_200 (SCC_OFFSET + 25)
+#define GPIO_201 (SCC_OFFSET + 26)
+#define GPIO_202 (SCC_OFFSET + 27)
+#define GPIO_203 (SCC_OFFSET + 28)
+#define GPIO_204 (SCC_OFFSET + 29)
+#define GPIO_205 (SCC_OFFSET + 30)
+#define GPIO_206 (SCC_OFFSET + 31)
+#define GPIO_207 (SCC_OFFSET + 32)
+#define GPIO_208 (SCC_OFFSET + 33)
+#define GPIO_209 (SCC_OFFSET + 34)
+#define TOTAL_SCC_PADS 35
+#define TOTAL_PADS (SCC_OFFSET + 35)
+
+
+#define PADBAR_OFFSET 0xC /* PAD BASE ADDRESS */
+
+
+/*
+ * Miscellaneous Configuration register(MISCCFG).These are community specific
+ * registers and are meant to house miscellaneous configuration fields per
+ * community. There are 8 GPIO groups: GPP_0 -> GPP_8 (Group 3 is absent)
+ */
+#define GPIO_MISCCFG 0x10 /* Miscellaneous Configuration offset */
+#define GPE_NW_31_0 0
+#define GPE_NW_63_32 1
+#define GPE_NW_79_64 2
+#define GPE_N_31_0 3
+#define GPE_N_63_32 4
+#define GPE_N_79_64 5
+#define GPE_AUDIO_19_0 6
+#define GPE_SCC_31_0 7
+#define GPE_SCC_34_32 8
+
+#define GPIO_MAX_NUM_PER_GROUP 32
+
+#define MISCCFG_GPE0_DW0_SHIFT 8
+#define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW0_SHIFT)
+#define MISCCFG_GPE0_DW1_SHIFT 12
+#define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
+#define MISCCFG_GPE0_DW2_SHIFT 16
+#define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT)
+
+/* Host Software Pad Ownership Register.
+ * The pins in the community are divided into 3 groups :
+ * GPIO 0 ~ 31, GPIO 32 ~ 63, GPIO 64 ~ 95
+ */
+#define HOSTSW_OWN_REG_0 0xB0
+
+#define GPI_INT_EN_0 0x110
+
+#define GPI_SMI_STS_0 0x170
+#define GPI_SMI_EN_0 0x190
+#define GPI_SMI_STS_OFFSET(group) (GPI_SMI_STS_0 + ((group) * 4))
+#define GPI_SMI_EN_OFFSET(group) (GPI_SMI_EN_0 + ((group) * 4))
+
+/* PERST_0 not defined */
+#define GPIO_PRT0_UDEF 0xFF
+
+#define NUM_NW_PADS (TOTAL_NW_PADS)
+#define NUM_N_PADS (TOTAL_N_PADS)
+#define NUM_AUDIO_PADS (TOTAL_AUDIO_PADS)
+#define NUM_SCC_PADS (TOTAL_SCC_PADS)
+
+#define NUM_NW_GPI_REGS \
+ (ALIGN_UP(NUM_NW_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_N_GPI_REGS \
+ (ALIGN_UP(NUM_N_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_AUDIO_GPI_REGS \
+ (ALIGN_UP(NUM_AUDIO_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_SCC_GPI_REGS \
+ (ALIGN_UP(NUM_SCC_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+
+#define NUM_GPI_STATUS_REGS (NUM_N_GPI_REGS + NUM_NW_GPI_REGS \
+ + NUM_AUDIO_GPI_REGS + NUM_SCC_GPI_REGS)
+
+
+/* Macros for translating a global pad offset to a local offset */
+#define PAD_NW(pad) (pad - NW_OFFSET)
+#define PAD_N(pad) (pad - N_OFFSET)
+#define PAD_AUDIO(pad) (pad - AUDIO_OFFSET)
+#define PAD_SCC(pad) (pad - SCC_OFFSET)
+
+/* Linux names of the GPIO devices. */
+#define GPIO_COMM_NW_NAME "INT3452:00"
+#define GPIO_COMM_N_NAME "INT3452:01"
+#define GPIO_COMM_AUDIO_NAME "INT3452:02"
+#define GPIO_COMM_SCC_NAME "INT3452:03"
+
+#define GPIO_18_IRQ 0x3C
+#define GPIO_21_IRQ 0x3F
+
+#define PAD_MODE_MASK 0x7
+
+#define PAD_CFG_BASE 0x600
+
+#ifndef __ACPI__
+struct gpi_status {
+ uint32_t grp[NUM_GPI_STATUS_REGS];
+};
+
+#endif /* __ACPI__ */
+#endif /* _SOC_GLk_GPIO_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/pci_apl_ids.h b/src/soc/intel/apollolake/include/soc/pci_apl_ids.h
new file mode 100644
index 0000000..c1649b2
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/pci_apl_ids.h
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_APOLLOLAKE_PCI_IDS_H_
+#define _SOC_APOLLOLAKE_PCI_IDS_H_
+
+#define PCI_DEVICE_ID_APOLLOLAKE_NB 0x5af0 /* 00:00.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_IGD_HD_505 0x5a84 /* 00:02.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_IGD_HD_500 0x5a85 /* 00:02.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_P2SB 0x5a92 /* 00:0d.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_PMC 0x5a94 /* 00:0d.1 */
+#define PCI_DEVICE_ID_APOLLOLAKE_HWSEQ_SPI 0x5a96 /* 00:0d.2 */
+#define PCI_DEVICE_ID_APOLLOLAKE_SRAM 0x5aec /* 00:0d.3 */
+#define PCI_DEVICE_ID_APOLLOLAKE_AUDIO 0x5a98 /* 00:0e.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_SATA 0x5ae0 /* 00:12.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_I2C0 0x5aac /* 00:16.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_I2C1 0x5aae /* 00:16.1 */
+#define PCI_DEVICE_ID_APOLLOLAKE_I2C2 0x5ab0 /* 00:16.2 */
+#define PCI_DEVICE_ID_APOLLOLAKE_I2C3 0x5ab2 /* 00:16.3 */
+#define PCI_DEVICE_ID_APOLLOLAKE_I2C4 0x5ab4 /* 00:17.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_I2C5 0x5ab6 /* 00:17.1 */
+#define PCI_DEVICE_ID_APOLLOLAKE_I2C6 0x5ab8 /* 00:17.2 */
+#define PCI_DEVICE_ID_APOLLOLAKE_I2C7 0x5aba /* 00:17.3 */
+#define PCI_DEVICE_ID_APOLLOLAKE_SPI0 0x5ac2 /* 00:19.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_SPI1 0x5ac4 /* 00:19.1 */
+#define PCI_DEVICE_ID_APOLLOLAKE_SPI2 0x5ac6 /* 00:19.2 */
+#define PCI_DEVICE_ID_APOLLOLAKE_LPC 0x5ae8 /* 00:1f.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_UART0 0x5abc /* 00:18.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_UART1 0x5abe /* 00:18.1 */
+#define PCI_DEVICE_ID_APOLLOLAKE_UART2 0x5ac0 /* 00:18.2 */
+#define PCI_DEVICE_ID_APOLLOLAKE_UART3 0x5aee /* 00:18.3 */
+#define PCI_DEVICE_ID_APOLLOLAKE_XHCI 0x5aa8 /* 00:15.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_XDCI 0x5aaa /* 00:15.1 */
+#endif /* _SOC_APOLLOLAKE_PCI_IDS_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/pci_glk_ids.h b/src/soc/intel/apollolake/include/soc/pci_glk_ids.h
new file mode 100644
index 0000000..baed4a8
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/pci_glk_ids.h
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_GLK_PCI_IDS_H_
+#define _SOC_GLK_PCI_IDS_H_
+
+#define PCI_DEVICE_ID_GLK_NB 0x31f0 /* 00:00.0 */
+#define PCI_DEVICE_ID_GLK_IGD 0x3184 /* 00:02.0 */
+#define PCI_DEVICE_ID_GLK_P2SB 0x3192 /* 00:0d.0 */
+#define PCI_DEVICE_ID_GLK_PMC 0x3194 /* 00:0d.1 */
+#define PCI_DEVICE_ID_GLK_HWSEQ_SPI 0x3196 /* 00:0d.2 */
+#define PCI_DEVICE_ID_GLK_AUDIO 0x3198 /* 00:0e.0 */
+#define PCI_DEVICE_ID_GLK_CSE0 0x5a9a /* 00:0f.0 */
+#define PCI_DEVICE_ID_HECI1 PCI_DEVICE_ID_GLK_CSE0
+#define PCI_DEVICE_ID_GLK_SATA 0x31e0 /* 00:12.0 */
+#define PCI_DEVICE_ID_GLK_XHCI 0x31a8 /* 00:15:0 */
+#define PCI_DEVICE_ID_GLK_XDCI 0x31aa /* 00:15:1 */
+#define PCI_DEVICE_ID_GLK_I2C0 0x31ac /* 00:16.0 */
+#define PCI_DEVICE_ID_GLK_I2C1 0x31ae /* 00:16.1 */
+#define PCI_DEVICE_ID_GLK_I2C2 0x31b0 /* 00:16.2 */
+#define PCI_DEVICE_ID_GLK_I2C3 0x31b2 /* 00:16.3 */
+#define PCI_DEVICE_ID_GLK_I2C4 0x31b4 /* 00:17.0 */
+#define PCI_DEVICE_ID_GLK_I2C5 0x31b6 /* 00:17.1 */
+#define PCI_DEVICE_ID_GLK_I2C6 0x31b8 /* 00:17.2 */
+#define PCI_DEVICE_ID_GLK_I2C7 0x31ba /* 00:17.3 */
+#define PCI_DEVICE_ID_GLK_UART0 0x31bc /* 00:18.0 */
+#define PCI_DEVICE_ID_GLK_UART1 0x31be /* 00:18.0 */
+#define PCI_DEVICE_ID_GLK_UART2 0x31c0 /* 00:18.0 */
+#define PCI_DEVICE_ID_GLK_UART3 0x31ee /* 00:18.0 */
+#define PCI_DEVICE_ID_GLK_SPI0 0x31c2 /* 00:19.0 */
+#define PCI_DEVICE_ID_GLK_SPI1 0x31c4 /* 00:19.1 */
+#define PCI_DEVICE_ID_GLK_SPI2 0x31c6 /* 00:19.2 */
+#define PCI_DEVICE_ID_GLK_SD 0x31ca /* 00:1b.0 */
+#define PCI_DEVICE_ID_GLK_LPC 0x31e8 /* 00:1f.0 */
+#endif /* _SOC_GLK_PCI_IDS_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h
index 25e7f94..2fe10df 100644
--- a/src/soc/intel/apollolake/include/soc/pci_ids.h
+++ b/src/soc/intel/apollolake/include/soc/pci_ids.h
@@ -1,8 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Intel Corp.
- * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ * Copyright (C) 2017 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -15,29 +14,10 @@
* GNU General Public License for more details.
*/
-#ifndef _SOC_APOLLOLAKE_PCI_IDS_H_
-#define _SOC_APOLLOLAKE_PCI_IDS_H_
+#ifndef _SOC_APL_PCI_IDS_H_
+#define _SOC_APL_PCI_IDS_H_
-#define PCI_DEVICE_ID_APOLLOLAKE_NB 0x5af0 /* 00:00.0 */
-#define PCI_DEVICE_ID_APOLLOLAKE_IGD_HD_505 0x5a84 /* 00:02.0 */
-#define PCI_DEVICE_ID_APOLLOLAKE_IGD_HD_500 0x5a85 /* 00:02.0 */
-#define PCI_DEVICE_ID_APOLLOLAKE_P2SB 0x5a92 /* 00:0d.0 */
-#define PCI_DEVICE_ID_APOLLOLAKE_PMC 0x5a94 /* 00:0d.1 */
-#define PCI_DEVICE_ID_APOLLOLAKE_HWSEQ_SPI 0x5a96 /* 00:0d.2 */
-#define PCI_DEVICE_ID_APOLLOLAKE_SRAM 0x5aec /* 00:0d.3 */
-#define PCI_DEVICE_ID_APOLLOLAKE_AUDIO 0x5a98 /* 00:0e.0 */
-#define PCI_DEVICE_ID_APOLLOLAKE_SATA 0x5ae0 /* 00:12.0 */
-#define PCI_DEVICE_ID_APOLLOLAKE_I2C0 0x5aac /* 00:16.0 */
-#define PCI_DEVICE_ID_APOLLOLAKE_I2C1 0x5aae /* 00:16.1 */
-#define PCI_DEVICE_ID_APOLLOLAKE_I2C2 0x5ab0 /* 00:16.2 */
-#define PCI_DEVICE_ID_APOLLOLAKE_I2C3 0x5ab2 /* 00:16.3 */
-#define PCI_DEVICE_ID_APOLLOLAKE_I2C4 0x5ab4 /* 00:17.0 */
-#define PCI_DEVICE_ID_APOLLOLAKE_I2C5 0x5ab6 /* 00:17.1 */
-#define PCI_DEVICE_ID_APOLLOLAKE_I2C6 0x5ab8 /* 00:17.2 */
-#define PCI_DEVICE_ID_APOLLOLAKE_I2C7 0x5aba /* 00:17.3 */
-#define PCI_DEVICE_ID_APOLLOLAKE_SPI0 0x5ac2 /* 00:19.0 */
-#define PCI_DEVICE_ID_APOLLOLAKE_SPI1 0x5ac4 /* 00:19.1 */
-#define PCI_DEVICE_ID_APOLLOLAKE_SPI2 0x5ac6 /* 00:19.2 */
-#define PCI_DEVICE_ID_APOLLOLAKE_LPC 0x5ae8 /* 00:1f.0 */
-
+#include <soc/pci_glk_ids.h>
+#include <soc/pci_apl_ids.h>
#endif /* _SOC_APOLLOLAKE_PCI_IDS_H_ */
+
diff --git a/src/soc/intel/apollolake/include/soc/pcr_ids.h b/src/soc/intel/apollolake/include/soc/pcr_ids.h
index b3e976e..ca5cf84 100644
--- a/src/soc/intel/apollolake/include/soc/pcr_ids.h
+++ b/src/soc/intel/apollolake/include/soc/pcr_ids.h
@@ -19,11 +19,16 @@
/*
* Port ids.
*/
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#define PID_GPIO_AUDIO 0xC9
+#define PID_GPIO_SCC 0xC8
+#else
#define PID_GPIO_SW 0xC0
#define PID_GPIO_S 0xC2
+#define PID_GPIO_W 0xC7
+#endif
#define PID_GPIO_NW 0xC4
#define PID_GPIO_N 0xC5
-#define PID_GPIO_W 0xC7
#define PID_ITSS 0xD0
#define PID_RTC 0xD1
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c
index 810c4c9..126d7b7 100644
--- a/src/soc/intel/apollolake/lpc.c
+++ b/src/soc/intel/apollolake/lpc.c
@@ -167,8 +167,14 @@
.scan_bus = scan_lpc_bus,
};
+static const unsigned short pci_device_ids[] = {
+ PCI_DEVICE_ID_APOLLOLAKE_LPC,
+ PCI_DEVICE_ID_GLK_LPC,
+ 0,
+};
+
static const struct pci_driver soc_lpc __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_APOLLOLAKE_LPC,
+ .devices = pci_device_ids,
};
diff --git a/src/soc/intel/apollolake/lpc_lib.c b/src/soc/intel/apollolake/lpc_lib.c
index 08c16a7..286679f 100644
--- a/src/soc/intel/apollolake/lpc_lib.c
+++ b/src/soc/intel/apollolake/lpc_lib.c
@@ -46,6 +46,17 @@
};
static const struct pad_config lpc_gpios[] = {
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+ PAD_CFG_NF(GPIO_147, UP_20K, DEEP, NF1), /* LPC_ILB_SERIRQ */
+ PAD_CFG_NF_IOS_1(GPIO_148, NONE, DEEP, NF1), /* LPC_CLKOUT0 */
+ PAD_CFG_NF_IOS_1(GPIO_149, NONE, DEEP, NF1), /* LPC_CLKOUT1 */
+ PAD_CFG_NF_IOS_1(GPIO_150, UP_20K, DEEP, NF1), /* LPC_AD0 */
+ PAD_CFG_NF_IOS_1(GPIO_151, UP_20K, DEEP, NF1), /* LPC_AD1 */
+ PAD_CFG_NF_IOS_1(GPIO_152, UP_20K, DEEP, NF1), /* LPC_AD2 */
+ PAD_CFG_NF_IOS_1(GPIO_153, UP_20K, DEEP, NF1), /* LPC_AD3 */
+ PAD_CFG_NF_IOS_1(GPIO_154, UP_20K, DEEP, NF1), /* LPC_CLKRUNB */
+ PAD_CFG_NF_IOS_1(GPIO_155, UP_20K, DEEP, NF1), /* LPC_FRAMEB*/
+#else
PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),
PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1),
PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1),
@@ -55,6 +66,7 @@
PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1),
PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1),
PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
+#endif
};
void lpc_configure_pads(void)
diff --git a/src/soc/intel/apollolake/northbridge.c b/src/soc/intel/apollolake/northbridge.c
index 9519603..28bbba1 100644
--- a/src/soc/intel/apollolake/northbridge.c
+++ b/src/soc/intel/apollolake/northbridge.c
@@ -162,8 +162,14 @@
.enable = DEVICE_NOOP
};
+static const unsigned short pci_device_ids[] = {
+ PCI_DEVICE_ID_APOLLOLAKE_NB,
+ PCI_DEVICE_ID_GLK_NB,
+ 0,
+};
+
static const struct pci_driver northbridge_driver __pci_driver = {
.ops = &northbridge_ops,
.vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_APOLLOLAKE_NB
+ .devices = pci_device_ids,
};
diff --git a/src/soc/intel/apollolake/p2sb.c b/src/soc/intel/apollolake/p2sb.c
index 8056d14..6fcd67a 100644
--- a/src/soc/intel/apollolake/p2sb.c
+++ b/src/soc/intel/apollolake/p2sb.c
@@ -67,8 +67,14 @@
.set_resources = DEVICE_NOOP,
};
+static const unsigned short pci_device_ids[] = {
+ PCI_DEVICE_ID_APOLLOLAKE_P2SB,
+ PCI_DEVICE_ID_GLK_P2SB,
+ 0,
+};
+
static const struct pci_driver pmc __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_APOLLOLAKE_P2SB,
+ .devices = pci_device_ids,
};
diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c
index ef39630..f0ed75d 100644
--- a/src/soc/intel/apollolake/pmc.c
+++ b/src/soc/intel/apollolake/pmc.c
@@ -164,8 +164,14 @@
.init = &pmc_init,
};
+static const unsigned short pci_device_ids[] = {
+ PCI_DEVICE_ID_APOLLOLAKE_PMC,
+ PCI_DEVICE_ID_GLK_PMC,
+ 0,
+};
+
static const struct pci_driver pmc __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_APOLLOLAKE_PMC,
+ .devices= pci_device_ids,
};
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 98c7015..641105b 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -119,6 +119,7 @@
*/
static bool punit_init(void)
{
+#if !IS_ENABLED(CONFIG_SOC_INTEL_GLK)
uint32_t reg;
uint32_t data;
struct stopwatch sw;
@@ -169,6 +170,9 @@
udelay(100);
}
return true;
+#else
+ return false;
+#endif
}
asmlinkage void car_stage_entry(void)
@@ -315,7 +319,9 @@
if (mrc_cache_get_current(MRC_VARIABLE_DATA, version, &rdev) == 0) {
/* Assume leaking is ok. */
assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED));
+#if !IS_ENABLED(CONFIG_SOC_INTEL_GLK) /* TODO */
mupd->FspmConfig.VariableNvsBufferPtr = rdev_mmap_full(&rdev);
+#endif
}
car_set_var(fsp_version, version);
diff --git a/src/soc/intel/apollolake/sd.c b/src/soc/intel/apollolake/sd.c
index 2f38061..7c96812 100644
--- a/src/soc/intel/apollolake/sd.c
+++ b/src/soc/intel/apollolake/sd.c
@@ -18,6 +18,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <soc/pci_ids.h>
#include <gpio.h>
#include "chip.h"
@@ -75,8 +76,14 @@
#endif
};
+static const unsigned short pci_device_ids[] = {
+ 0x5aca,
+ PCI_DEVICE_ID_GLK_SD,
+ 0,
+};
+
static const struct pci_driver pch_sd __pci_driver = {
.ops = &dev_ops,
.vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x5aca
+ .devices= pci_device_ids,
};
diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c
index 311e580..947d908 100644
--- a/src/soc/intel/apollolake/uart_early.c
+++ b/src/soc/intel/apollolake/uart_early.c
@@ -37,10 +37,15 @@
}
static const struct pad_config uart_gpios[] = {
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+ PAD_CFG_NF_IOS_1(GPIO_64, UP_20K, DEEP, NF1), /* LPSS_UART2_RXD */
+ PAD_CFG_NF_IOS_1(GPIO_65, UP_20K, DEEP, NF1), /* LPSS_UART2_TXD */
+#else
PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */
PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* UART1 TX */
PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX */
PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */
+#endif
};
void pch_uart_init(void)
@@ -49,7 +54,11 @@
device_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
/* Get a 0-based pad index. See invalid_uart_for_console() above. */
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+ const int pad_index = 0;
+#else
const int pad_index = CONFIG_UART_FOR_CONSOLE - 1;
+#endif
if (invalid_uart_for_console())
return;
--
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Gerrit-MessageType: newchange
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