[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Enable decoding for ComA and ComB on LPC

[Mario Scheithauer (Code Review)]

Mario Scheithauer has uploaded a new change for review. ( https://review.coreboot.org/19693 )

Change subject: soc/intel/apollolake: Enable decoding for ComA and ComB on LPC
......................................................................

soc/intel/apollolake: Enable decoding for ComA and ComB on LPC

If there is an external 8250 UART, one needs to enable the appropriate
address ranges before console_init() is called so that the init sequence
can reach the external UART.
Furthermore FSPM needs different settings for an external UART port. For
this, the function fill_console_params() have to adapt.

Change-Id: I62c7d0b54edd18acf793849aef352afbcaeb68b9
Signed-off-by: Mario Scheithauer <mario.scheithauer at siemens.com>
---
M src/soc/intel/apollolake/include/soc/lpc.h
M src/soc/intel/apollolake/romstage.c
2 files changed, 35 insertions(+), 9 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/19693/1

diff --git a/src/soc/intel/apollolake/include/soc/lpc.h b/src/soc/intel/apollolake/include/soc/lpc.h
index 7e3d74a..a40e362 100644
--- a/src/soc/intel/apollolake/include/soc/lpc.h
+++ b/src/soc/intel/apollolake/include/soc/lpc.h
@@ -29,8 +29,9 @@
  * IO decode enable macros are in the format IO_<peripheral>_<IO port>.
  * For example, to open ports 0x60, 0x64 for the keyboard controller,
  * use IOE_KBC_60_64 macro. For IOE_ macros that do not specify a port range,
- * the port range is selectable via the IO decodes register (not referenced).
+ * the port range is selectable via the IO decodes register.
  */
+#define REG_IO_DECODE			0x80
 #define REG_IO_ENABLES			0x82
 #define  IOE_EC_4E_4F			(1 << 13)
 #define  IOE_SUPERIO_2E_2F		(1 << 12)
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 98c7015..4386995 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -35,6 +35,7 @@
 #include <soc/cpu.h>
 #include <soc/intel/common/mrc_cache.h>
 #include <soc/iomap.h>
+#include <soc/lpc.h>
 #include <soc/systemagent.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
@@ -85,6 +86,17 @@
 	/* Enable decoding for HPET. Needed for FSP global pointer storage */
 	pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
 						P2SB_HPTC_ADDRESS_ENABLE);
+
+	if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) {
+		/*
+		 * I/O Decode Range Register for LPC
+		 * ComA Range 3F8h-3FFh
+		 * ComB Range 2F8h-2FF
+		 */
+		pci_write_config16(PCH_DEV_LPC, REG_IO_DECODE, 0x0010);
+		/* Enable ComA and ComB Port */
+		lpc_enable_fixed_io_ranges(IOE_COMA_EN | IOE_COMB_EN);
+	}
 }
 
 static void disable_watchdog(void)
@@ -245,14 +257,27 @@
 static void fill_console_params(FSPM_UPD *mupd)
 {
 	if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) {
-		mupd->FspmConfig.SerialDebugPortDevice =
-			CONFIG_UART_FOR_CONSOLE;
-		/* use MMIO port type */
-		mupd->FspmConfig.SerialDebugPortType = 2;
-		/* use 4 byte register stride */
-		mupd->FspmConfig.SerialDebugPortStrideSize = 2;
-		/* used only for port type set to external */
-		mupd->FspmConfig.SerialDebugPortAddress = 0;
+		if (IS_ENABLED(CONFIG_SOC_UART_DEBUG)) {
+			mupd->FspmConfig.SerialDebugPortDevice =
+					CONFIG_UART_FOR_CONSOLE;
+			/* use MMIO port type */
+			mupd->FspmConfig.SerialDebugPortType = 2;
+			/* use 4 byte register stride */
+			mupd->FspmConfig.SerialDebugPortStrideSize = 2;
+			/* used only for port type set to external */
+			mupd->FspmConfig.SerialDebugPortAddress = 0;
+		}
+		if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) {
+			/* use external UART for debug */
+			mupd->FspmConfig.SerialDebugPortDevice = 3;
+			/* use I/O port type */
+			mupd->FspmConfig.SerialDebugPortType = 1;
+			/* use 1 byte register stride */
+			mupd->FspmConfig.SerialDebugPortStrideSize = 0;
+			/* used only for port type set to external */
+			mupd->FspmConfig.SerialDebugPortAddress =
+					CONFIG_TTYS0_BASE;
+		}
 	} else {
 		mupd->FspmConfig.SerialDebugPortType = 0;
 	}

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I62c7d0b54edd18acf793849aef352afbcaeb68b9
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Mario Scheithauer <mario.scheithauer at siemens.com>